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Exploiting Different Levels of Parallelism in the Quantum Control Microarchitecture for Superconducting Qubits
arXiv - CS - Emerging Technologies Pub Date : 2021-08-19 , DOI: arxiv-2108.08671
Mengyu Zhang, Lei Xie, Zhenxing Zhang, Qiaonian Yu, Guanglei Xi, Huangliang Zhang, Fuming Liu, Yarui Zheng, Yicong Zheng, Shengyu Zhang

As current Noisy Intermediate Scale Quantum (NISQ) devices suffer from decoherence errors, any delay in the instruction execution of quantum control microarchitecture can lead to the loss of quantum information and incorrect computation results. Hence, it is crucial for the control microarchitecture to issue quantum operations to the Quantum Processing Unit (QPU) in time. As in classical microarchitecture, parallelism in quantum programs needs to be exploited for speedup. However, three challenges emerge in the quantum scenario: 1) the quantum feedback control can introduce significant pipeline stall latency; 2) timing control is required for all quantum operations; 3) QPU requires a deterministic operation supply to prevent the accumulation of quantum errors. In this paper, we propose a novel control microarchitecture design to exploit Circuit Level Parallelism (CLP) and Quantum Operation Level Parallelism (QOLP). Firstly, we develop a Multiprocessor architecture to exploit CLP, which supports dynamic scheduling of different sub-circuits. This architecture can handle parallel feedback control and minimize the potential overhead that disrupts the timing control. Secondly, we propose a Quantum Superscalar approach that exploits QOLP by efficiently executing massive quantum instructions in parallel. Both methods issue quantum operations to QPU deterministically. In the benchmark test of a Shor syndrome measurement, a six-core implementation of our proposal achieves up to 2.59$\times$ speedup compared with a single core. For various canonical quantum computing algorithms, our superscalar approach achieves an average of 4.04$\times$ improvement over a baseline design. Finally, We perform a simultaneous randomized benchmarking (simRB) experiment on a real QPU using the proposed microarchitecture for validation.

中文翻译:

在超导量子位的量子控制微架构中利用不同级别的并行性

由于当前的噪声中级量子 (NISQ) 设备存在退相干错误,量子控制微架构的指令执行中的任何延迟都可能导致量子信息的丢失和错误的计算结果。因此,控制微架构及时向量子处理单元 (QPU) 发出量子操作至关重要。与经典微体系结构一样,需要利用量子程序中的并行性来加速。然而,量子场景中出现了三个挑战:1) 量子反馈控制会引入显着的流水线延迟延迟;2)所有量子操作都需要时序控制;3) QPU 需要一个确定性的操作供给来防止量子误差的积累。在这篇论文中,我们提出了一种新颖的控制微架构设计,以利用电路级并行 (CLP) 和量子操作级并行 (QOLP)。首先,我们开发了一个多处理器架构来利用 CLP,它支持不同子电路的动态调度。这种架构可以处理并行反馈控制,并将破坏时序控制的潜在开销降至最低。其次,我们提出了一种量子超标量方法,该方法通过有效地并行执行大量量子指令来利用 QOLP。这两种方法都确定性地向 QPU 发出量子操作。在 Shor 综合征测量的基准测试中,与单核相比,我们建议的六核实现实现了高达 2.59 倍的加速。对于各种规范的量子计算算法,我们的超标量方法比基线设计平均提高了 4.04$\times$。最后,我们使用提议的微架构对真实 QPU 进行同步随机基准测试 (simRB) 实验以进行验证。
更新日期:2021-08-20
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