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Critical Path Tube Redundancy for Power Minimization in CNFET Circuits With Variations
IEEE Transactions on Nanotechnology ( IF 2.4 ) Pub Date : 2021-07-27 , DOI: 10.1109/tnano.2021.3100467
Satya Keerthi Vendra , Malgorzata Chrzanowska-Jeske

Tube redundancy and correlation has been proposed to increase the functional yield of CNFET-based circuits under CNT variations. However, adding redundant-CNTs is associated with increased power and sometimes increased area. The impact of CNT correlation on CNFET-based circuit performance also remains unexplored. Adding redundancy to all transistors in a circuit was considered in many works. In this paper, we propose adding an optimized number of redundant tubes only to transistors on critical paths. The optimized number of redundant-CNTs is pre-calculated for a desired functional yield. We show that this restricted redundancy retains the improved delay-limited yield achieved in circuits with redundant-CNTs added to all transistors. Moreover, this limited redundancy also reduces power dissipation without exceeding the allowed delay degradation. To ensure redundant tubes are added to all transistors on all critical paths which can emerge in all fabricated circuits due to CNT variations, those paths must first be identified. We propose an efficient method to identify all the critical paths that can exist in the presence of CNT variations. With uncorrelated-CNFETs, our approach reduces the average power increase by 7.8% as compared to all-transistor redundancy. Results also show an improvement in critical path delay by 15–20% and up to 10% reduction in allowed delay-degradation. To examine the influence of tube correlation on CNFET-based circuit performance, two correlated-CNFET standard-cell layouts are evaluated. An average increase of 1.8X in critical path delay variation due to CNFET correlation is noticed in a set of ISCAS’85 benchmarks.

中文翻译:

具有变化的 CNFET 电路中功率最小化的关键路径管冗余

已经提出了管冗余和相关性,以在 CNT 变化下提高基于 CNFET 的电路的功能产量。然而,添加冗余碳纳米管会增加功率,有时还会增加面积。CNT 相关性对基于 CNFET 的电路性能的影响也仍未得到探索。许多作品都考虑过为电路中的所有晶体管添加冗余。在本文中,我们建议仅向关键路径上的晶体管添加优化数量的冗余管。冗余 CNT 的优化数量是为所需的功能产量预先计算的。我们表明,这种受限制的冗余保留了在将冗余 CNT 添加到所有晶体管的电路中实现的改进的延迟限制产量。此外,这种有限的冗余还能在不超过允许的延迟降级的情况下降低功耗。为了确保将冗余管添加到所有关键路径上的所有晶体管,这些路径可能因 CNT 变化而出现在所有制造电路中,必须首先识别这些路径。我们提出了一种有效的方法来识别存在 CNT 变化时可能存在的所有关键路径。对于不相关的 CNFET,与全晶体管冗余相比,我们的方法将平均功率增加降低了 7.8%。结果还显示,关键路径延迟改善了 15-20%,允许的延迟降级减少了 10%。为了检查管相关性对基于 CNFET 的电路性能的影响,评估了两种相关的 CNFET 标准单元布局。在一组 ISCAS'85 基准测试中注意到,由于 CNFET 相关性,关键路径延迟变化平均增加了 1.8 倍。
更新日期:2021-08-20
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