System efficient electrostatic discharge (ESD) design is an effective method for simulating the ESD behaviors of a system. Based on this simulation method, this article mainly investigates the transient behaviors of a system-level ESD protection circuit with and without a 2.5 V power supply. During power- on state, latch-up levels of a feedback power clamp protected by off-chip elements are predicted and mainly analyzed under machine model stress. During power- off state, the physical failure of a hybrid-triggered power clamp under surge stress is investigated. In addition to the utilization of transmission line pulsing (TLP) I-V curves, transient TLP waveforms are also used for building the component models in the system-level ESD protection circuit. Moreover, the relevant measurements for the power- on state and power- off state are included in this article for verifying the simulation results. For ESD designers, this article provides a complete modeling and analysis process of co-design protection circuit to investigate the electrical behaviors.

中文翻译：

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上下电系统级静电放电保护建模研究

系统高效静电放电 (ESD) 设计是一种模拟系统 ESD 行为的有效方法。基于这种仿真方法，本文主要研究了系统级ESD保护电路在有和没有2.5 V电源的情况下的瞬态行为。通电期间—— 状态下，由片外元件保护的反馈电源钳位的闩锁水平被预测并主要在机器模型应力下进行分析。通电期间—— 关闭状态下，研究了混合触发电源钳位在浪涌应力下的物理故障。除了利用传输线脉冲 (TLP)IV 曲线、瞬态 TLP 波形也用于构建系统级 ESD 保护电路中的组件模型。此外，功率的相关测量 关于国家和权力—— 关闭状态包含在本文中以验证仿真结果。对于 ESD 设计人员，本文提供了完整的协同设计保护电路建模和分析过程，以研究电气行为。