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A Rail-to-Rail Topology for CMOS Neuron Cells with Analog Inputs-Output and Digital Weights
International Journal of Electronics ( IF 1.3 ) Pub Date : 2021-09-09 , DOI: 10.1080/00207217.2021.1969440
Fabian L. Cabrera 1 , Tiago O. Weber 2
Affiliation  

ABSTRACT

In this article we propose a new CMOS(complementary metal–oxide–semiconductor) neuron topology with analog signals and digital weights. An arrangement of series transconductors multiply the input voltage by the digital weights resulting in weighted currents. These currents can be added or subtracted from the output node. The output current flows through a resistance generating the output voltage. Since the voltage signals are rail-to-rail, the non-linear function of the neuron is naturally obtained by the saturation of the output near ground and supply voltages. The proposed topology is promising for neuromorphic systems as it uses voltage-mode to interconnect different neurons and current-mode for the internal processing (applying a straight-forward computation strategy for neurons). The neuron is designed in CMOS 180 nm, when considering an one-input neuron it occupies and active area of 490 µm 2 and has a maximum power consumption of 4.7 µW while achieving an operating frequency of 100 kHz. A simple network with three neurons (each one with three inputs) is designed to confirm the proper functionality of the system. The resulting average power per synapse is lower than the one-input cell due to the reduced consumption for some weights and the occupied active area per synapse is also lower because some blocks are not scaled for multiple synapses. On the other hand, the frequency response worsens because the capacitance of the additional input circuits.



中文翻译:

具有模拟输入输出和数字权重的 CMOS 神经元单元的轨到轨拓扑

摘要

在本文中,我们提出了一种具有模拟信号和数字权重的新型 CMOS(互补金属氧化物半导体)神经元拓扑。串联跨导器的布置将输入电压乘以数字权重,从而产生加权电流。可以从输出节点添加或减去这些电流。输出电流流过产生输出电压的电阻。由于电压信号是轨到轨的,神经元的非线性函数自然是通过输出接近地和电源电压的饱和来获得的。所提出的拓扑对于神经形态系统很有前景,因为它使用电压模式来互连不同的神经元,并使用电流模式来进行内部处理(对神经元应用直接的计算策略)。神经元采用 CMOS 180 nm 设计,微米_ 2最大功耗为 4.7 µW,工作频率为 100 kHz。具有三个神经元(每个神经元具有三个输入)的简单网络旨在确认系统的正确功能。由于某些权重的消耗减少,每个突触的平均功率低于单输入单元,并且每个突触占用的活动区域也较低,因为某些块没有针对多个突触进行缩放。另一方面,由于附加输入电路的电容,频率响应变差。

更新日期:2021-09-09
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