In this paper, a shift register (SR) memory based on rapid single flux quantum (RSFQ) logic for bit-parallel access is proposed. The memory cell changes from a row in the memory array to a column to increase the bit of data accessed per one clock cycle. The design of the 8 bit 2 bit (8 2) memory is introduced. The memory consists of four parts: a SR memory array, an input buffer, an output buffer, and a controller, in which the controller is used to produce a control signal at a certain clock cycle specified by the address data. We have obtained the low speed test of the 8 2 memory fabricated by 6 kA cm⁻² Nb process (SIMIT-Nb03), all bit-parallel access operations (write, read, clear and write, and read again) have been verified. We also simulated the 8 8 memory with data width expansion and obtained the maximum operating frequency of 34 GHz after the place and route with the SIMIT-Nb03 cell library. Based on the hierarchical storage, we have used the 8 8 memory as a basic block to construct large size of memory system, the access time and bandwidth have been evaluated. The bit-parallel memory shows higher bandwidth than bit-serial memory with the same capacity, especially for large capacity memory.

在本文中，提出了一种基于快速单通量量子 (RSFQ) 逻辑的用于位并行访问的移位寄存器 (SR) 存储器。存储单元从存储阵列中的一行变为一列，以增加每个时钟周期访问的数据位。介绍了8位2位（8位2）内存的设计。存储器由四部分组成：SR存储器阵列、输入缓冲器、输出缓冲器和控制器，其中控制器用于在地址数据指定的某个时钟周期产生控制信号。我们已经获得了 6 kA cm ^-2制造的 8 2 存储器的低速测试Nb进程（SIMIT-Nb03），所有位并行访问操作（写、读、清写、再读）均已验证。我们还模拟了数据宽度扩展的 8 8 内存，并使用 SIMIT-Nb03 单元库进行布局布线后获得了 34 GHz 的最大工作频率。在分层存储的基础上，我们以8×8内存为基本块构建了大容量内存系统，对访问时间和带宽进行了评估。位并行存储器比相同容量的位串行存储器显示出更高的带宽，特别是对于大容量存储器。