Surging interest in engineering quantum computers has stimulated significant and focused research on technologies needed to make them manufacturable and scalable. In the ion trap realm this has led to a transition from bulk three-dimensional macro-scale traps to chip-based ion traps and included important demonstrations of passive and active electronics, waveguides, detectors, and other integrated components. At the same time as these technologies are being developed the system sizes are demanding more ions to run noisy intermediate scale quantum (NISQ) algorithms, growing from around ten ions today to potentially a hundred or more in the near future. To realize the size and features needed for this growth, the geometric and material design space of microfabricated ion traps must expand. In this paper we describe present limitations and the approaches needed to overcome them, including how geometric complexity drives the number of metal levels, why routing congestion affects the size and location of shunting capacitors, and how RF power dissipation can limit the size of the trap array. We also give recommendations for future research needed to accommodate the demands of NISQ scale ion traps that are integrated with additional technologies.

人们对工程量子计算机的兴趣激增，激发了对使其可制造和可扩展所需技术的重要且集中的研究。在离子阱领域，这导致了从块状三维宏观尺度阱到基于芯片的离子阱的转变，包括对无源和有源电子、波导、探测器和其他集成组件的重要演示。在开发这些技术的同时，系统规模需要更多离子来运行嘈杂的中尺度量子 (NISQ) 算法，从今天的大约十个离子增加到不久的将来可能会增加到一百个或更多。为了实现这种增长所需的尺寸和特征，微制造离子阱的几何和材料设计空间必须扩大。在本文中，我们描述了目前的限制以及克服这些限制所需的方法，包括几何复杂性如何驱动金属层的数量，为什么布线拥塞会影响分流电容器的大小和位置，以及 RF 功耗如何限制陷阱的大小大批。我们还为满足与其他技术集成的 NISQ 级离子阱需求所需的未来研究提供建议。