With the aggressive growth of the internet of things-based applications in the domestic and industrial domain, the embedded static memory is also under renovation stage to eliminate classical barriers such as soft errors, poor stability, and mediocre performance. In this work, a novel twelve transistors (12T) SRAM cell is presented that replaces the conventional inverter with Schmitt trigger-based inverter in core latch. The proposed SRAM circuit has been compared with four formerly reported designs for investigating the improvement in terms of various performance metrics. These designs include conventional six transistors (6T), tunable transistor 8T (T8T), PPN inverter-based 10T (PP10T), and stable low read power 11T (S11T) cells. The presented cell effectively minimizes the soft errors attributed to 1.36×/1.27×/1.66×/1.27× enhancement of critical charge compared to 6T/T8T/PP10T/S11T cells. Also, the proposed bit-cell effectively mitigates multi-bit-cell upsets because it allows bit interleaving array structure. The presented bit-cell also shows reduction in leakage power by 1.08×/1.33×/0.43×/1.28× in comparison to 6T/T8T/PP10T/S11T cells, respectively. The read and write stability of proposed bit-cell circuit is enhanced by 1.96×/1.88×/1×/1.92× and 1.15×/1.19×/1.29×/1.45×, respectively, in comparison to 6T/T8T/PP10T/S11T cells, respectively. In addition to this, proposed cell exhibits improvement in dynamic power, data retention voltage, and overall electrical quality matrix. Variability comparison of key design metrics such as read power and read current of the proposed SRAM circuit with 6T cell has also been presented in this work.

中文翻译：

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具有改进的临界电荷的稳定 12T SRAM 的表征

随着基于物联网的应用在国内和工业领域的迅猛增长，嵌入式静态存储器也处于更新阶段，以消除软错误、稳定性差、性能平庸等经典障碍。在这项工作中，提出了一种新颖的十二晶体管 (12T) SRAM 单元，它在核心锁存器中用基于施密特触发器的反相器代替了传统的反相器。所提出的 SRAM 电路已与之前报道的四种设计进行了比较，以研究各种性能指标方面的改进。这些设计包括传统的六晶体管 (6T)、可调晶体管 8T (T8T)、基于 PPN 反相器的 10T (PP10T) 和稳定的低读取功率 11T (S11T) 单元。所提出的单元有效地最小化了归因于的软错误1.36×/1.27×/1.66×/1.27×与 6T/T8T/PP10T/S11T 电池相比，临界电荷增强。此外，所提出的位单元有效地减轻了多位单元干扰，因为它允许位交错阵列结构。所呈现的位单元还显示出泄漏功率降低了1.08×/1.33×/0.43×/1.28×分别与 6T/T8T/PP10T/S11T 细胞相比。所提出的位单元电路的读写稳定性通过以下方式增强1.96×/1.88×/1×/1.92×和1.15×/1.19×/1.29×/1.45×，分别与 6T/T8T/PP10T/S11T 细胞相比。除此之外，所提出的电池在动态功率、数据保持电压和整体电气质量矩阵方面都表现出改进。在这项工作中还提出了关键设计指标的可变性比较，例如所提出的具有 6T 单元的 SRAM 电路的读取功率和读取电流。