ABSTRACT

Memristor-based combinational logic is one of the unique concepts of designing digital circuits to achieve compact design, faster operation, and lesser power consumption. This work presents a unique memristor-based transistor-less combinational logic circuits design and analyses the performance benchmarking with other state of the art methods. Observed results demonstrated that the proposed design performs comparatively well in terms of size, speed, and power consumption. Basic combinational logic circuits, such as full adder, multiplexer, decoder, and priority encoder are being designed using the University of Michigan Model. The basic logic gates which include AND, OR, XOR are also designed using the concept of memristor ratioed logic. The proposed design of full adder utilises 14 memristors and 2 inverters, the delay time is 26.5ps, and power consumption is 0.5nW which is less compared to the other design. The proposed 4 × 1 multiplexer, 2-to-4 decoder and 4-to-2 priority encoder consume 0.6nW, 0.15nW, and 0.87nW power respectively. The observed improvement in these significant parameters demonstrates the potential of using memristor-based transistor-less combinational logic circuits in modern electronic devices.

摘要

基于忆阻器的组合逻辑是设计数字电路以实现紧凑设计、更快操作和更低功耗的独特概念之一。这项工作提出了一种独特的基于忆阻器的无晶体管组合逻辑电路设计，并使用其他最先进的方法分析了性能基准测试。观察结果表明，所提出的设计在尺寸、速度和功耗方面表现相对较好。基本组合逻辑电路，例如全加器、多路复用器、解码器和优先级编码器，正在使用密歇根大学模型进行设计。包括与、或、异或在内的基本逻辑门也是使用忆阻器比例逻辑的概念设计的。提出的全加器设计采用14个忆阻器和2个反相器，延迟时间为26.5ps，功耗为 0.5nW，与其他设计相比更低。所提出的 4 × 1 多路复用器、2 对 4 解码器和 4 对 2 优先编码器分别消耗 0.6nW、0.15nW 和 0.87nW 的功率。观察到的这些重要参数的改进证明了在现代电子设备中使用基于忆阻器的无晶体管组合逻辑电路的潜力。