This paper analyzes the mechanism by which Single-Event-Upsets (SEUs) and Single-Event-transients (SETs) impact on the working condition of the charge-pump-phase-locked-loop (CPPLL) and relevant hardened techniques, and also presents a soft-error-tolerant CPPLL in 40 nm CMOS process. It employs dual-mode interlocking (DMI) and divider-resistance techniques to reduce the soft-error rate caused by natural irradiation. Simulation and laser test results reveal that the DMI and divider resistance techniques could effectively decrease the number of SEU-sensitive nodes in digital parts (frequency divider, phase, and frequency detector) and SET-sensitive nodes in charge pumps. Under 960pJ laser energy, the number of SEU-sensitive nodes in digital parts decreases 96.1%; the number of SET-sensitive nodes in charge pump decline by 83.1%. The proposed soft-error-tolerant CPPLL operates under a 1.1 V power supply, consumes 16.6 mW of power, and achieves 1.25 GHz - 3.125 GHz working frequency range, 3.18 ps RMS-jitter at a 2.5GHz output frequency.

本文分析了Single-Event-Upsets (SEUs)和Single-Event-transients (SETs)对电荷泵锁相环(CPPLL)和相关硬化技术工作条件的影响机制，以及提出了采用 40 nm CMOS 工艺的软错误容错 CPPLL。它采用双模式互锁 (DMI) 和分压电阻技术来降低自然辐射引起的软错误率。仿真和激光测试结果表明，DMI 和分压器电阻技术可以有效减少数字部件（分频器、相位和频率检测器）中的 SEU 敏感节点和电荷泵中的 SET 敏感节点的数量。960pJ激光能量下，数字部分SEU敏感节点减少96.1%；电荷泵中SET敏感节点的数量下降了83.1%。