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Performance Optimization of Analog Circuits in Negative Capacitance Transistor Technology
Microelectronics Journal ( IF 2.2 ) Pub Date : 2021-08-05 , DOI: 10.1016/j.mejo.2021.105193
Om Prakash 1 , Nitanshu Chauhan 2 , Aniket Gupta 2 , Hussam Amrouch 3
Affiliation  

Negative Capacitance Field-Effect Transistor (NC-FET) is one of the emerging technology for the future ultra-low power circuits. NC-FET incorporates a ferroelectric layer within the transistor gate stack, which provides an internal voltage amplification. However, Negative Differential Resistance (NDR), which occurs at thick ferroelectric can deteriorate NC-FET devices in which the drain current, in the saturation region, decreases with drain voltage increase. This noticeably harms the figure of merits of circuits, especially when it comes to analog applications.

This work presents a detailed analysis on the correlation between ferroelectric thickness and NDR effects using well-calibrated TCAD infrastructure for 14 nm FDSOI. For the first time, a novel extension length modulation technique is proposed to mitigate NDR effects effectively. Our technique allows designers to optimize the combination of ferroelectric thickness and extension length in which NDR effects are well suppressed, thereby maximizing the performance and gain of analog circuits.



中文翻译:

负电容晶体管技术中模拟电路的性能优化

负电容场效应晶体管(NC-FET)是未来超低功耗电路的新兴技术之一。NC-FET 在晶体管栅极堆叠内加入了铁电层,提供内部电压放大。然而,在厚铁电体上出现的负差分电阻 (NDR) 会损坏 NC-FET 器件,其中饱和区的漏极电流随着漏极电压的增加而降低。这明显损害了电路的品质因数,尤其是在模拟应用方面。

这项工作使用针对 14 nm FDSOI 的经过良好校准的 TCAD 基础设施,详细分析了铁电体厚度与 NDR 效应之间的相关性。首次提出了一种新的扩展长度调制技术来有效减轻 NDR 效应。我们的技术使设计人员能够优化铁电体厚度和延伸长度的组合,从而很好地抑制 NDR 效应,从而最大限度地提高模拟电路的性能和增益。

更新日期:2021-08-12
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