To minimize the area of analog-to-digital converters (ADCs) for multichannel applications and break the SNDR limitation caused by DAC-induced nonlinearity, a more area-efficient mismatch error shaping (MES) scheme is proposed in noise shaping (NS) successive-approximation (SAR) ADC. By employing a switched-capacitor (SC) voltage divider, the proposed method makes the flash ADC and data weighted averaging (DWA) digital circuits in the original MES method obsolete. Therefore, the complexity of the architecture is highly reduced, and the area is significantly reduced to 0.037 mm ² . In addition, the power consumption for the MES implementation is significantly decreased by more than 7.3%. The proposed SAR ADC is fabricated in GF 40-nm CMOS technology. The measurements show that the proposed MES technique improves the SFDR from 64 to 102 dB and decreases the THD from −63.6 to −95.7 dB. The SNR and SNDR in a 20-kHz bandwidth are 91.6 and 90.2 dB, respectively. The power consumption is $383.4~\mu \text{W}$ with a 1.1-V power supply at a 16-MS/s sampling rate.

中文翻译：

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具有失配误差整形技术的面积效率型 SAR ADC 在 20kHz 带宽上实现 102dB SFDR 90.2dB SNDR

为了最大限度地减少多通道应用的模数转换器 (ADC) 的面积并打破由 DAC 引起的非线性引起的 SNDR 限制，在噪声整形 (NS) 中提出了面积效率更高的失配误差整形 (MES) 方案) 逐次逼近 (SAR) ADC。通过采用开关电容器 (SC) 分压器，所提出的方法使原始 MES 方法中的闪存 ADC 和数据加权平均 (DWA) 数字电路过时。因此，架构复杂度大幅降低，面积大幅缩减至0.037 mm ² . 此外，MES 实施的功耗显着降低了 7.3% 以上。建议的 SAR ADC 采用 GF 40-nm CMOS 技术制造。测量结果表明，所提出的 MES 技术将 SFDR 从 64 dB 提高到 102 dB，并将 THD 从 -63.6 dB 降低到 -95.7 dB。20 kHz 带宽中的 SNR 和 SNDR 分别为 91.6 和 90.2 dB。耗电量为 $ 383.4 ~ \ mu \ text {W} $ 使用 1.1-V 电源，采样率为 16-MS/s。