This brief proposes hardware-friendly QC-LDPC decoding algorithm with layered scheduling based on new logarithmic-likelihood-ratio compound (LLRC) segregation technique. Subsequently, we present hardware-efficient QC-LDPC decoder-architecture based on the proposed algorithm and additional architectural optimizations. This decoder has been designed based on the 5G-NR specifications, supporting code-lengths and code-rates in the ranges of 26112–10368 bits and 1/3–8/9, respectively. Performance analysis has shown that suggested LLRC-segregation based decoding algorithm delivers adequate FER of 10 ⁻⁵ between 1 to 6.5 dB of SNR range. Furthermore, proposed QC-LDPC decoder is post-route simulated and implemented on the FPGA platform. It operates at a maximum clock frequency of 135 MHz and delivers a peak throughput of 11.02 Gbps. Eventually, comparison with relevant works shows that our decoder delivers $2.2\times $ higher throughput and $8.3\times $ better hardware-efficiency than the state-of-the-art implementations.

中文翻译：

---

基于硬件效率和高吞吐量 LLRC 分离的二进制 QC-LDPC 解码算法和架构

本简介基于新的对数似然比复合 (LLRC) 分离技术提出了具有分层调度的硬件友好的 QC-LDPC 解码算法。随后，我们基于所提出的算法和其他架构优化提出了硬件高效的 QC-LDPC 解码器架构。该解码器基于 5G-NR 规范设计，支持码长和码率范围分别为 26112-10368 位和 1/3-8/9。性能分析表明，建议的基于 LLRC 隔离的解码算法提供了 10 ^{-5 的}足够 FER SNR 范围在 1 到 6.5 dB 之间。此外，提出的 QC-LDPC 解码器在 FPGA 平台上进行了路由后仿真和实现。它以 135 MHz 的最大时钟频率运行，并提供 11.02 Gbps 的峰值吞吐量。最终，与相关作品的比较表明，我们的解码器提供了 $2.2\times $ 更高的吞吐量和 $8.3\times $ 比最先进的实现更好的硬件效率。