Optical probing, though developed as silicon debugging tools from the chip backside, has shown its capability of extracting secret data, such as cryptographic keys and user identifications, from modern system-on-chip devices. Existing optical probing countermeasures are based on detecting any device modification attempt or abrupt change in operating conditions during asset extraction. These countermeasures usually require additional fabrication steps and cause area and power overheads. In this article, we propose a novel low-overhead design methodology to prevent optical probing. It leverages additional operational logic gates, termed as “CONCEALING-Gates,” inserted as neighbor gates of the logic gates connected to the nets carrying asset signals. The switching activity of the asset carrying logic is camouflaged with the switching activity of the concealing-gate. The input signal and placement in the layout of the concealing-gates must be selected in such a way that they remain equally effective in preventing different variants of optical probing, i.e., electro-optical frequency mapping and Electro-optical probing. The methodology is suitable for the existing ASIC/FPGA design flow and fabrication process, since designing new standard logic cells is not required. We have performed a comprehensive security evaluation of the concealing-gates using a security metric developed based on the parameters that are crucial for optical probing. The attack resiliency of the logic cells, protected by concealing-gates, is evaluated using an empirical study-based simulation methodology and experimental validation. Our analysis has shown that in the presence of concealing-gates, logic cells achieve high resiliency against optical contactless probing techniques.

中文翻译：

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CONCEALING-Gate：光学非接触式探测弹性设计

光学探测虽然是作为芯片背面的硅调试工具而开发的，但已显示出其从现代片上系统设备中提取秘密数据（例如加密密钥和用户标识）的能力。现有的光学探测对策基于在资产提取期间检测任何设备修改尝试或操作条件的突然变化。这些对策通常需要额外的制造步骤并导致面积和功率开销。在本文中，我们提出了一种新颖的低开销设计方法来防止光学探测。它利用额外的操作逻辑门，称为“隐藏门”，作为连接到承载资产信号的网络的逻辑门的相邻门插入。资产承载逻辑的切换活动被隐藏门的切换活动伪装。必须以这样的方式选择输入信号和隐藏门布局中的位置，以使它们在防止光学探测的不同变体（即电光频率映射和电光探测）方面保持同样有效。该方法适用于现有的 ASIC/FPGA 设计流程和制造过程，因为不需要设计新的标准逻辑单元。我们使用基于对光学探测至关重要的参数开发的安全指标对隐藏门进行了全面的安全评估。由隐藏门保护的逻辑单元的攻击弹性，使用基于经验研究的模拟方法和实验验证进行评估。我们的分析表明，在存在隐藏门的情况下，逻辑单元对光学非接触式探测技术具有很高的弹性。