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FreqCounter: Efficient Cacheability of Encryption and Integrity Tree Counters in Secure Processors
Journal of Systems Architecture ( IF 4.5 ) Pub Date : 2021-07-30 , DOI: 10.1016/j.sysarc.2021.102252
Omais Shafi 1 , Janibul Bashir 1
Affiliation  

The data in the off-chip main memory can be potentially extracted or tampered by an adversary having physical access to the device and thus it becomes inevitable to secure the data present in the off-chip memory. The modern designs consider storing the counters on-chip to prevent replay attacks. However, these designs have significant overheads in terms of the on-chip storage used to store counters, and the additional execution time.

In this paper, we propose a new mechanism FreqCounter that trims the on-chip storage by storing the counters blockwise in a tag array on-chip cache rather than in a page-wise manner as is conventionally done. The counters for only those blocks are maintained that are expected to miss frequently in the last level cache (LLC). We show that the FreqCounter reduces the space overheads compared to prior schemes by 53.02% keeping performance almost similar if not better. We further show that our design reduces the ED2 by 14.5% on an average compared to the recent competing scheme Morphable Counters without any compromise in the security.



中文翻译:

FreqCounter:安全处理器中加密和完整性树计数器的高效缓存能力

片外主存储器中的数据可能会被对设备进行物理访问的对手提取或篡改,因此保护片外存储器中存在的数据变得不可避免。现代设计考虑将计数器存储在芯片上以防止重放攻击。然而,这些设计在用于存储计数器的片上存储和额外的执行时间方面具有显着的开销。

在本文中,我们提出了一种新机制FreqCounter,它通过将计数器按块存储在标签阵列片上缓存中而不是像传统那样以页方式存储来调整片上存储。仅维护那些预计在最后一级缓存 (LLC) 中经常丢失的块的计数器。我们表明,与之前的方案相比,FreqCounter减少了 53.02% 的空间开销,保持性能几乎相似,甚至更好。我们进一步表明,我们的设计减少了 ED2与最近的竞争方案Morphable Counters相比,平均提高了 14.5% ,而且安全性没有任何妥协。

更新日期:2021-08-20
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