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Low-Latency Lattice-Reduction-Aided One-Bit Precoding Processor for 64-QAM 4×64 MU–MIMO Systems
IEEE Open Journal of Circuits and Systems Pub Date : 2021-07-26 , DOI: 10.1109/ojcas.2021.3087482
Pao-Pao Ho , Chiao-En Chen , Yuan-Hao Huang

Massive multi-user multiple-input multiple-output (MU-MIMO) communication is a crucial technique for next-generation wireless systems because it enables high-throughput and ultra-reliable data transmission. However, high power consumption is a challenging problem in conventional transceiver designs, where each RF chain at the transmitter requires a pair of high-resolution digital-to-analog converters (DACs), which are the primary power sources in front-end circuits. Therefore, quantized precoding algorithms were recently proposed to address this issue. They used low-resolution DACs at the transmitter and compensated for the distortion caused by the quantization effect at the baseband. This paper proposes a constellation-range gain-controlled lattice-reduction-aided (CR-GCLRA) one-bit precoding algorithm for massive MU-MIMO systems with high-order quadrature amplitude modulation (QAM) signaling. Lattice reduction (LR) preprocessing is adopted for performance enhancement. A novel gain-control mechanism is proposed to address the constellation range expansion problem in conventional LR preprocessing. We designed and implemented a CR-GCLRA one-bit precoding processor by using TSMC 40-nm CMOS technology to accelerate the one-bit precoding processing for 64-QAM $4 \times 64$ MU-MIMO system. The proposed one-bit precoding processor can achieve a throughput of 43.92 Mbits per second at a clock speed of 269 MHz with 271 mW power consumption and $0.51\mu \text{s}$ latency.

中文翻译:

用于 64-QAM 4×64 MU-MIMO 系统的低延迟点阵缩减辅助一位预编码处理器

大规模多用户多输入多输出 (MU-MIMO) 通信是下一代无线系统的一项关键技术,因为它可以实现高吞吐量和超可靠的数据传输。然而,在传统收发器设计中,高功耗是一个具有挑战性的问题,其中发射器的每个 RF 链都需要一对高分辨率数模转换器 (DAC),它们是前端电路中的主要电源。因此,最近提出了量化预编码算法来解决这个问题。他们在发射机上使用了低分辨率 DAC,并补偿了基带量化效应造成的失真。本文针对具有高阶正交幅度调制 (QAM) 信令的大规模 MU-MIMO 系统提出了一种星座范围增益控制的格约化辅助 (CR-GCLRA) 一位预编码算法。采用格子约简 (LR) 预处理来增强性能。提出了一种新的增益控制机制来解决传统LR预处理中的星座范围扩展问题。我们设计并实现了 CR-GCLRA 一位预编码处理器,采用 TSMC 40-nm CMOS 技术加速 64-QAM 的一位预编码处理 $4 \times 64$ MU-MIMO 系统。所提出的一位预编码处理器可以在 269 MHz 的时钟速度和 271 mW 的功耗下实现每秒 43.92 Mbits 的吞吐量和 $0.51\mu\text{s}$ 潜伏。
更新日期:2021-07-27
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