This article presents a $4\times $ time-interleaved (TI) 2nd-order discrete-time (DT) delta-sigma modulator (DSM). We propose a digital feed-forward extrapolation by first digitizing the internal analog nodes’ information from one channel, and then extrapolating the other channels in the digital domain. As a result, this DSM only needs two operational amplifiers (op-amps) to realize four interleaving paths, thus reducing analog hardware overheads. Meanwhile, we linearize the digital feed-forward paths through injected dithering. We present the derivation of extrapolating TI DSM starting from a single-channel DSM, while we also list and compare several conventional TI approaches. Implemented in 28-nm CMOS, this modulator achieves an equivalent output-sampling rate of 2.08 GS/s, $208\times $ oversampling ratio (OSR), and a signal to noise and distortion ratio (SNDR)/spurious-free dynamic range (SFDR) of 86.1 dB/98 dB with 5-MHz bandwidth (BW). The power consumption is 23.1 mW, which results in a Schreier Figure of Merit (FoM) of 169.5 dB.

中文翻译：

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使用数字前馈外推实现 5MHz 带宽和 86.1dB SNDR 的时间交错二阶 ΔΣ 调制器

这篇文章提出了一个 $4\times $ 时间交错 (TI) 二阶离散时间 (DT) Δ-Σ 调制器 (DSM)。我们提出了一种数字前馈外推，首先数字化来自一个通道的内部模拟节点的信息，然后外推数字域中的其他通道。因此，该 DSM 只需要两个运算放大器（op-amps）即可实现四个交错路径，从而减少模拟硬件开销。同时，我们通过注入抖动将数字前馈路径线性化。我们展示了从单通道 DSM 开始外推 TI DSM 的推导，同时我们还列出并比较了几种传统的 TI 方法。该调制器采用 28 纳米 CMOS 实现，可实现 2.08 GS/s 的等效输出采样率， $208\次 $ 过采样率 (OSR)，以及 5-MHz 带宽 (BW) 的 86.1 dB/98 dB 的信噪比和失真比 (SNDR)/无杂散动态范围 (SFDR)。功耗为 23.1 mW，这导致 Schreier 品质因数 (FoM) 为 169.5 dB。