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A 51-pJ/Pixel 33.7-dB PSNR 4× Compressive CMOS Image Sensor With Column-Parallel Single-Shot Compressive Sensing
IEEE Journal of Solid-State Circuits ( IF 5.4 ) Pub Date : 2021-05-06 , DOI: 10.1109/jssc.2021.3071875
Chanmin Park , Wenda Zhao , Injun Park , Nan Sun , Youngcheol Chae

This article presents a CMOS image sensor (CIS) with column-parallel single-shot compressive sensing (CS) for always-on Internet-of-Things (IoT) application, which achieves an energy efficiency of 51 pJ/pixel, while maintaining high image quality of PSNR > 33.7 dB and SSIM > 0.89. This is enabled by an energy-efficient encoder, which replaces a densely populated CS encoding matrix with a highly sparse pseudo-diagonal one. Since the proposed column-parallel CS encoder can be implemented directly at pixel outputs with an energy-efficient switched-capacitor matrix multiplier, data compression is achieved prior to the pixel digitization, thereby greatly reducing ADC power, data size, and I/O power. The energy efficiency of the image sensor is further improved by using dynamic single-slope ADCs. A prototype VGA image sensor implemented in a 110-nm CMOS process consumes only 0.7 mW at 45 frames/s. The corresponding energy per pixel (51 pJ/pixel) amounts to more than $5\times $ improvement over the previous low-energy benchmark for CS image sensors.

中文翻译:

具有列并行单次压缩传感的 51pJ/像素 33.7dB PSNR 4× 压缩 CMOS 图像传感器

本文介绍了一种具有列平行单次压缩传感 (CS) 的 CMOS 图像传感器 (CIS),用于永远在线的物联网 (IoT) 应用,可实现 51 pJ/像素的能效,同时保持高PSNR > 33.7 dB 和 SSIM > 0.89 的图像质量。这是由节能编码器实现的,该编码器用高度稀疏的伪对角线代替了密集填充的 CS 编码矩阵。由于所提出的列并行 CS 编码器可以直接在像素输出处使用节能开关电容器矩阵乘法器实现,因此在像素数字化之前实现数据压缩,从而大大降低 ADC 功率、数据大小和 I/O 功率. 使用动态单斜率 ADC 进一步提高了图像传感器的能效。在 110 纳米 CMOS 工艺中实现的原型 VGA 图像传感器在 45 帧/秒时仅消耗 0.7 mW。每像素对应的能量(51 pJ/像素)超过 $5\times $ 对之前 CS 图像传感器的低能耗基准的改进。
更新日期:2021-05-06
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