Although multirow read is essential to achieve static random access memory (SRAM) in-memory computing (IMC), it may undermine circuit linearity and computational consistency across columns. In this study, we investigated the causes of nonlinearity and inconsistency. Based on detailed analyses, we proposed a cascade current mirror (CCM) peripheral circuit. Only four transistors were added to each bitline (BL) for voltage clamping and proportionally mirroring the read current. In addition, a 6T SRAM cell with double word lines operating with the CCM further reduced the delay and improved the computational consistency. We applied the structure to numerous prior studies and evaluated them using the 28-nm complementary metal–oxide semiconductor process. The measurement results show that the proposed CCM can reduce the integer nonlinearity by up to 70% at 0.8-V supply, and the computational consistency is substantially improved by 56.84% at 0.9-V supply. In addition, we verified the performance improvement through classification using a convolutional neural network, achieving 91% accuracy in the MNIST and 86% accuracy in the CIFAR-10. The area overhead was 1.77% in a $512\times512$ SRAM array when integrating the proposed CCM circuit.

中文翻译：

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级联电流镜以提高 SRAM 内存计算中的线性度和一致性

尽管多行读取对于实现静态随机存取存储器 (SRAM) 内存计算 (IMC) 至关重要，但它可能会破坏跨列的电路线性度和计算一致性。在这项研究中，我们调查了非线性和不一致的原因。基于详细分析，我们提出了级联电流镜（CCM）外围电路。每条位线 (BL) 上仅添加了四个晶体管，用于电压钳位和按比例镜像读取电流。此外，带有双字线的 6T SRAM 单元与 CCM 一起运行，进一步降低了延迟并提高了计算一致性。我们将该结构应用于许多先前的研究，并使用 28 纳米互补金属氧化物半导体工艺对其进行评估。测量结果表明，所提出的 CCM 在 0.8-V 电源下可以将整数非线性降低多达 70%，并且在 0.9-V 电源下计算一致性显着提高了 56.84%。此外，我们使用卷积神经网络通过分类验证了性能改进，在 MNIST 中实现了 91% 的准确度，在 CIFAR-10 中实现了 86% 的准确度。面积开销为 1.77% $512\times512$ 集成建议的 CCM 电路时的 SRAM 阵列。