Accurately modeling memory timing in a processor simulator is crucial for obtaining accurate and useful performance predictions. DRAM has a complex timing and reordering scheme, which results in highly varying access latencies depending on the type of operations, address stream patterns and bandwidth load. Therefore, DRAM simulators model the DRAM timings as a clocked state machine. However, some processor simulators, in particular loosely synchronized parallel simulators, assume an immediate-response memory model, requesting an immediate estimation of the memory latency. In this letter, we discuss the modeling issues in transforming a state machine DRAM simulator into an immediate-response simulator, which can be directly plugged into a processor simulator supporting an immediate-response memory model and/or a relaxed parallel simulation model. We show that the adapted model is accurate within 2 percent compared to the state machine simulator.

中文翻译：

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使用即时响应存储器模型在并行模拟器中模拟 DRAM 时序

在处理器模拟器中准确建模内存时序对于获得准确且有用的性能预测至关重要。DRAM 具有复杂的时序和重新排序方案，这会导致访问延迟高度不同，具体取决于操作类型、地址流模式和带宽负载。因此，DRAM 模拟器将 DRAM 时序建模为时钟状态机。然而，一些处理器模拟器，特别​​是松散同步的并行模拟器，采用即时响应内存模型，要求立即估计内存延迟。在这封信中，我们讨论了将状态机 DRAM 模拟器转换为即时响应模拟器的建模问题，该模拟器可以直接插入支持即时响应内存模型和/或宽松并行模拟模型的处理器模拟器中。