Analog discrete cosine transform (DCT) with CMOS image sensor is an advantageous alternative in low power wireless Compressed Sensing (CS) Systems. The researchers have made some attempts in the recent past behind analog 2D-DCT using switched-capacitor (SC) and current mirror that follow conventional cascaded DCT technique. But these techniques lack accuracy due to capacitor mismatch and circuit-level noises on the DCT symbol. This approach presents a novel algorithm (using product-to-sum method and periodicity of cosine function) to obtain a computational block for current-mode circuit realization of 2D-DCT in a single stage. Cascoded current mirror in the circuit ensures higher accuracy in computation. Rigorous simulation of proposed circuit in SPICE with 65 nm CMOS process showed the supremacy of the architecture. The power consumption can be kept minimal to 12.1 mW for 8*8 2-D DCT during the computation of 64 output symbols using conventional class-AB current mirror. With dynamic biasing strategy, this can be reduced to even less than 3 mW. The circuit simulated DCT symbols were tested in a CS block model at different compression ratios (CR).

带有 CMOS 图像传感器的模拟离散余弦变换 (DCT) 是低功耗无线压缩传感 (CS) 系统中的一种有利替代方案。最近，研究人员在使用开关电容器 (SC) 和电流镜的模拟 2D-DCT 背后进行了一些尝试，遵循传统的级联 DCT 技术。但是，由于电容器不匹配和 DCT 符号上的电路级噪声，这些技术缺乏准确性。这种方法提出了一种新颖的算法（使用乘积求和方法和余弦函数的周期性）来获得用于在单个阶段中实现 2D-DCT 的电流模式电路的计算块。电路中的级联电流镜确保了更高的计算精度。在 SPICE 中使用 65 nm CMOS 工艺对所提出的电路进行了严格的模拟，显示了该架构的优越性。在使用传统的 AB 类电流镜计算 64 个输出符号期间，8*8 2-D DCT 的功耗可以保持在 12.1 mW。使用动态偏置策略，这甚至可以减少到 3 mW 以下。电路模拟的 DCT 符号在 CS 块模型中以不同的压缩比 (CR) 进行了测试。