In this letter, for the first time, we investigate the role of Ferroelectric (FE) spacer in a negative capacitance (NC) FinFET. Using well-calibrated TCAD models, we found that instead of placing a dielectric (DE) spacer, if we use an FE spacer, enhanced electric field due to FE polarization can be achieved, thereby producing a higher ON-current. The fringing fields polarize the FE spacer and result in voltage amplification, which lowers the effective barrier and increases the current driving capability. ON-current of the proposed configuration, i.e., FE spacer at the source (S) side and DE spacer at the drain (D) side, is ~30% higher than the baseline FinFET. In this work, we have also proposed four different spacer placement configurations to realize better performances in terms of higher ON-current, mitigation of negative differential resistance (NDR) and better subthreshold slope (SS), and so on. We found that the optimized performance can be attained by placing an FE and DE spacer at the S and D end, respectively. We also evaluated a design space window for a good capacitance match to achieve NC effect for optimized device design.

中文翻译：

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一种具有铁电间隔物的新型负电容 FinFET：提案和调查。

在这封信中，我们首次研究了铁电 (FE) 间隔物在负电容 (NC) FinFET 中的作用。使用经过良好校准的 TCAD 模型，我们发现，如果我们使用 FE 垫片，而不是放置电介质 (DE) 垫片，则可以实现由于 FE 极化而产生的增强电场，从而产生更高的导通电流。边缘场极化FE间隔物并导致电压放大，从而降低有效势垒并增加电流驱动能力。所提议配置的导通电流，即源极 (S) 侧的 FE 隔离物和漏极 (D) 侧的 DE 隔离物，比基线 FinFET 高约 30%。在这项工作中，我们还提出了四种不同的垫片放置配置，以在更高的导通电流方面实现更好的性能，减轻负微分电阻 (NDR) 和更好的亚阈值斜率 (SS)，等等。我们发现，通过分别在 S 和 D 端放置 FE 和 DE 垫片可以实现优化的性能。我们还评估了一个设计空间窗口以获得良好的电容匹配，以实现优化器件设计的 NC 效果。