Integration ( IF 1.9 ) Pub Date : 2021-07-15 , DOI: 10.1016/j.vlsi.2021.05.013 Amir Hossein Kazemi 1 , Mohsen Hayati 1
In this paper, a Low Noise Amplifier (LNA) with the current reused topology is proposed for wideband applications. To increase input impedance matching common source with inductive degeneration and RC shunt feedback structure is used. To extend the bandwidth, inductive series peaking technique is utilized. In the next stage, two parallel structure is hired to have a high voltage gain with low power consumption in addition to improve linearity. Also, by using the self-forward-body-bias (SFBB) technique, supply voltage is reduced and as a result power consumption is decreased further. The proposed LNA exhibits the high and flat gain of 14.7–15.4 dB, input return loss of less than −11 dB and noise figure range of 2.3–4.4 dB from 1 GHz up to 8 GHz. It consumes 5.4 mW from a 1.2 V power supply. The achieved IIP3 range for the proposed LNA is 0 dBm up to +2.7 dBm. The proposed LNA occupies 0.45 mm2 in 0.18-μm CMOS technology.
中文翻译:
采用改进的前馈结构的电流复用结构的平坦增益线性低噪声放大器的设计与分析
在本文中,针对宽带应用提出了一种具有当前重用拓扑结构的低噪声放大器 (LNA)。为了增加输入阻抗匹配共源与电感退化和 RC 分流反馈结构被使用。为了扩展带宽,使用了电感串联峰化技术。下一阶段采用两个并联结构,除了提高线性度外,还具有高电压增益和低功耗。此外,通过使用自前向体偏置 (SFBB) 技术,降低了电源电压,从而进一步降低了功耗。提议的 LNA 表现出 14.7–15.4 dB 的高且平坦的增益,小于 -11 dB 的输入回波损耗和 2.3-4.4 dB 的噪声系数范围(从 1 GHz 到 8 GHz)。它从 1.2 V 电源消耗 5.4 mW。建议的 LNA 实现的 IIP3 范围为 0 dBm 至 +2.7 dBm。建议的 LNA 占用 0.45 mm2英寸 0.18 微米 CMOS 技术。