In-memory-computing (IMC) architecture has been proposed as an alternative to cope with the memory wall of von-Neumann computing architecture. The IMC architecture embeds logic into the memory array to reduce the data transfer between the processor and memory. An IMC memory can be operated in memory mode and computing mode, which increases the test complexity. Thus, the IMC memory need to be tested in memory mode and computing mode. In this paper, we propose a test strategy for IMC 8 T SRAMs with NAND and NOR logic operations. Possible functional faults caused by the isolated read port of the 8 T SRAM cell are analyzed. A 12N March C⁻⁸ test algorithm is proposed to cover functional faults in memory mode and process variation-induced faults in computing mode of an N-bit IMC 8 T SRAM. Extendibility of the proposed test strategy for 8 T SRAMs and multiple operands is shown as well.

内存计算 (IMC) 架构已被提议作为应对冯诺依曼计算架构内存墙的替代方案。IMC 架构将逻辑嵌入到内存阵列中，以减少处理器和内存之间的数据传输。IMC内存可以在内存模式和计算模式下运行，这增加了测试的复杂性。因此，IMC内存需要在内存模式和计算模式下进行测试。在本文中，我们为具有 NAND 和 NOR 逻辑运算的 IMC 8 T SRAM 提出了一种测试策略。分析了由 8 T SRAM 单元的隔离读取端口引起的可能功能故障。提出了一种12 N March C ^-8测试算法来覆盖内存模式中的功能故障和N的计算模式中的过程变化引起的故障。位 IMC 8 T SRAM。还显示了针对 8 T SRAM 和多个操作数的建议测试策略的可扩展性。