The main idea of this article is to propose a hardware design of block matching (BM) algorithm for an efficient motion estimation (ME) strategy in a field programmable gate array platform based on a parallel implemented genetic algorithm (GA). Easiness and the effectiveness of the BM algorithm while implementing have a major drawback of low quality and computationally cost expensive during the process of ME. Therefore, here in this article, we suggest GA based BM for a quick and cost-effective computation of motion vectors, without negotiating the quality factor. The ME carried out for various video sequences is implemented by using Xilinx ISE Design Suite 14.1. Delay, time, area, power, PSNR, MSE, SNR, SSIM, and NRMSE are the metrics used for analyzing the performance, and the simulation outcome shows that this parallel implemented BM architecture design shows an exotic improvement in time, quality and in utilization of power on estimating the motion than that of the conventional designs.

中文翻译：

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一种高效的基于现场可编程门阵列的硬件架构，用于通过并行实现的遗传算法进行高效的运动估计

本文的主要思想是在基于并行实现的遗传算法 (GA) 的现场可编程门阵列平台中，提出一种用于有效运动估计 (ME) 策略的块匹配 (BM) 算法的硬件设计。BM 算法在实现过程中的简单性和有效性具有在 ME 过程中质量低和计算成本昂贵的主要缺点。因此，在本文中，我们建议使用基于 GA 的 BM 来快速且经济高效地计算运动矢量，而无需协商品质因数。为各种视频序列执行的 ME 是通过使用 Xilinx ISE 设计套件 14.1 实现的。延迟、时间、面积、功率、PSNR、MSE、SNR、SSIM 和 NRMSE 是用于分析性能的指标，