This paper proposes a Differential-Input Body Bias Sense Amplifier (DIBBSA) with an auto-offset mitigation feature suitable for low-voltage SRAMs where the differential bitline signals are applied to the sources as well as to the body of the critical sensing transistors. We simulated and fabricated the proposed DIBBSA architecture with various operational modes in 65-nm CMOS technology to analyze body biasing’s effectiveness in mitigating the offset. The standard deviation of offset ( $\boldsymbol {\sigma }_{\mathbf {OS}}$ ) was measured over 5120 SAs in 10 ICs. The iso-gate area reduction in $\boldsymbol {\sigma }_{\mathbf {OS}}$ for the proposed DIBBSA-FL and DIBBSA-PD modes resulted in 68.1% and 61.9% compared to conventional Current Latch SA (CLSA) and 24.1% and 18.1% compared to Voltage Latch SA (VLSA) at 0.4 V supply and 25 °C, respectively. Carried out measurements on 512 SAs in an IC show the minimum required differential input voltage across the temperature range of 0 °C to 75 °C at 0.4 V is achieved to be 48% lower compared to CLSA and 28% lower compared to VLSA by both the DIBBSA-FL and DIBBSA-PD modes.

中文翻译：

---

具有用于低压 SRAM 的自动偏移缓解功能的体偏置感测放大器

本文提出了一种具有自动偏移缓解功能的差分输入体偏置感测放大器 (DIBBSA)，适用于低压 SRAM，其中差分位线信号应用于源极以及关键感测晶体管的主体。我们在 65 纳米 CMOS 技术中模拟并制造了具有各种操作模式的拟议 DIBBSA 架构，以分析体偏置在减轻偏移方面的有效性。偏移的标准偏差（ $\boldsymbol {\sigma }_{\mathbf {OS}}$ ) 测量了 10 个 IC 中的 5120 个 SA。等栅面积减少 $\boldsymbol {\sigma }_{\mathbf {OS}}$ 对于提议的 DIBBSA-FL 和 DIBBSA-PD 模式，在 0.4 V 电源和 25 °C 下，与传统电流锁存 SA (CLSA) 相比分别提高了 68.1% 和 61.9%，与电压锁存 SA (VLSA) 相比分别提高了 24.1% 和 18.1%，分别。对 IC 中的 512 个 SA 进行的测量表明，在 0°C 至 75°C 的温度范围内，0.4 V 所需的最小差分输入电压比 CLSA 低 48%，比 VLSA 低 28% DIBBSA-FL 和 DIBBSA-PD 模式。