This paper proposes an area, speed and power-optimized band-pass digital signal processing filter targeted for Kintex-7 Field Programmable Gate Array device. The filter was designed using MATLAB and Simulink and code generated using HDL Coder from MathWorks. The implementation was created using a novel high-level synthesis design method, which reduces pessimism associated with bit-width constraints in synthesis for inputs, outputs, and intermediate data nodes. MATLAB HDL coder generated Register Transfer Level (RTL) code was implemented on Xilinx Kintex 7 using Vivado software. The obtained results are superior to those of previous implementations for exact filter specifications. We also performed an RTL simulation for the filter and compared the functional verification results with a golden double-precision implementation in MATLAB. The results suggest that constraining the bit width and pessimism reduction has less than 1% impact on the filter accuracy within limits specified by architecture specifications.

本文提出了一种针对 Kintex-7 现场可编程门阵列器件的面积、速度和功率优化的带通数字信号处理滤波器。滤波器使用 MATLAB 和 Simulink 设计，代码使用 MathWorks 的 HDL Coder 生成。该实现是使用一种新颖的高级综合设计方法创建的，该方法减少了与输入、输出和中间数据节点的综合中的位宽约束相关的悲观情绪。MATLAB HDL 编码器生成的寄存器传输级 (RTL) 代码使用 Vivado 软件在 Xilinx Kintex 7 上实现。对于精确的滤波器规格，获得的结果优于先前实现的结果。我们还对滤波器进行了 RTL 仿真，并将功能验证结果与 MATLAB 中的黄金双精度实现进行了比较。