Thermal resistance (R_th) is an important design parameter for high power integrated circuits (ICs). Evaluation of R_th is particularly complicated for FETs in CMOS silicon-on-insulator (SOI) technology. Although the buried oxide underneath FETs in CMOS ICs presents a barrier to heat flow, the interconnect metals and surrounding oxide provide additional paths for heat-sinking. This paper describes simulations of the layout-dependent R_th of FETs in a CMOS-SOI IC including the interconnect effects, and experimental measurements that support the simulated results. The simulation technique used is an adaptation of a commercial electromagnetic solver, EMX, to heat flow. Simulation results show that in representative layouts with power FETs the heat flow via interconnects accounts for 50 to 70% of the overall heat flow in typical microwave and millimeter-wave ICs. Analytical results are presented to allow estimation of various R_th contributions. Experimental measurements are reported using I-V characteristics of a p-n diode to monitor the temperature of an FET, in good agreement with the analysis. Guidelines for the reduction of R_th are discussed. A layout technique for reducing R_th of an FET is described, and demonstrated experimentally by I-V measurements. The benefit of vias through the buried oxide is highlighted.

热阻 (R _th ) 是高功率集成电路 (IC) 的重要设计参数。对于 CMOS 绝缘体上硅 (SOI) 技术中的 FET ，R _{th 的}评估特别复杂。尽管 CMOS IC 中 FET 下方的掩埋氧化物为热流提供了障碍，但互连金属和周围的氧化物为散热提供了额外的路径。本文描述了与布局相关的 R _{th 的}仿真CMOS-SOI IC 中的 FET，包括互连效应，以及支持模拟结果的实验​​测量。所使用的模拟技术是商业电磁求解器 EMX 对热流的改编。仿真结果表明，在具有功率 FET 的代表性布局中，通过互连产生的热流占典型微波和毫米波 IC 总热流的 50% 至 70%。提供了分析结果以允许估计各种 R _th贡献。实验测量报告使用 pn 二极管的 IV 特性来监测 FET 的温度，与分析非常一致。讨论了降低 R _{th 的}指南。一种降低 R _{th 的}布局技术描述了 FET，并通过 IV 测量进行了实验证明。突出了通过掩埋氧化物的通孔的好处。