Approximate computing is a striking approach to design area-efficient low-power datapath units for fault buoyant applications. This brief presents the design of a novel 4: 2 approximate compressor that generates no error in the carry signal. The proposed compressor is employed for partial product (PP) compression in two variants of Dadda multiplier to see its effectiveness in error-resilient image and signal processing applications. In the targeted multipliers, the approximate 4:2 compressor is used in the least n PP columns, while the exact counterpart is used in the remaining most significant columns, and hence the maximum error is precisely maintained within 2ⁿ. PP compression is performed in stages using the Wallace approach, and the final two rows of sum and carry signals are added using a ripple carry adder in the basic design. In the proposed multiplier design-2, we do not generate sum bits in the approximate part. However, the proposed error-tolerant compressor is used in appropriate columns to propagate carry to the least significant column in the exact part. Performance evaluations using Cadence Encounter with 90 nm application specific integrated circuit technology revealed that the proposed-full width (P-FW) and the proposed-truncated (P-Trun) approximate multipliers demonstrate 22.7% and 32.4% power-delay product reduction compared to the standard multiplier. Implementations of the proposed multipliers in signal and image processing applications revealed superior performance in terms of accuracy compared to prior similar approximate designs.

近似计算是为故障浮力应用设计面积高效的低功耗数据路径单元的一种引人注目的方法。本简介介绍了一种新颖的 4:2 近似压缩器的设计，该压缩器不会在进位信号中产生错误。建议的压缩器用于在 Dadda 乘法器的两种变体中进行部分积 (PP) 压缩，以查看其在容错图像和信号处理应用中的有效性。在目标乘法器中，在最少 n 个 PP 列中使用近似 4:2 压缩器，而在其余最重要的列中使用精确对应的压缩器，因此最大误差精确地保持在 2 ⁿ以内. PP 压缩使用 Wallace 方法分阶段执行，最后两行和和进位信号在基本设计中使用纹波进位加法器相加。在提议的乘法器设计 2 中，我们不在近似部分生成和位。然而，建议的容错压缩器在适当的列中使用以将进位传播到精确部分中的最低有效列。使用 Cadence Encounter 和 90 nm 专用集成电路技术进行的性能评估表明，与建议的全宽 (P-FW) 和建议的截断 (P-Trun) 近似乘法器相比，功率延迟积降低了 22.7% 和 32.4%。标准乘数。