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Temperature assessment of Si1-xGex source/drain heterojunction NT-JLFET for gate induced drain leakage ‒ A compact model
Micro and Nanostructures ( IF 3.1 ) Pub Date : 2021-07-03 , DOI: 10.1016/j.spmi.2021.106961
Anchal Thakur 1 , Rohit Dhiman 1
Affiliation  

In this paper, we have investigated the impact of temperature (T) and drain bias voltage (Vds) on gate induced drain leakage (GIDL) in SiGe Source/Drain heterojunction silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET). We developed a temperature dependent model for surface potential, electric field EZ, L-BTBT induced IGIDL and full drain current Ids using 2-D Poison equation with suitable boundary conditions. We have also examined impact of temperature (activation energy) and drain bias voltage (electric field) on L-BTBT induced IGIDL. It is found that the increase in drain bias voltage causes 31.1% rise in IGIDL and elevation in temperature has 29.4% increase in IGIDL. Furthermore, we have examined impact of temperature on transconductance (gm) and output conductance (gd). The results demonstrated that temperature and drain bias voltage has significant impact on SiGe S/D NTJLFET, however, it is considerably less than the NTJLFET.



中文翻译:

Si 1-x Ge x源极/漏极异质结 NT-JLFET 的栅极诱导漏极泄漏的温度评估‒ 紧凑模型

在本文中,我们研究了温度 ( T ) 和漏极偏置电压 ( V ds ) 对 SiGe 源极/漏极异质结硅纳米管无结场效应晶体管 (S/D Si-NT) 中栅极感应漏极泄漏 (GIDL) 的影响JLFET)。我们使用具有合适边界条件的 2-D Poison 方程开发了表面电位、电场E Z、L-BTBT 感应I GIDL和全漏电流I ds的温度相关模型。我们还研究了温度(活化能)和漏极偏置电压(电场)对 L-BTBT 诱导的I GIDL 的影响. 发现漏极偏置电压的增加导致I GIDL增加31.1% ,温度升高导致I GIDL增加29.4% 。此外,我们还研究了温度对跨导 ( g m ) 和输出电导 ( g d ) 的影响。结果表明,温度和漏极偏置电压对 SiGe S/D NTJLFET 有显着影响,但远小于 NTJLFET。

更新日期:2021-07-08
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