Ultrathin equivalent oxide thickness (EOT) scaling of TiN/Y ₂ O ₃ /SiGe gate stacks using a trimethylaluminum (TMA) treatment was studied. In comparison to previously reported high-k/SiGe MOS interfaces utilizing various Ge contents, we obtained an EOT scaling down to 1 nm with ultralow interface trap densities ( $\text{D}_{\text {it}}$ ). In addition, the impact of EOT scaling on the SiGe MOS interface properties has been investigated. We found the stress-induced degradation at the SiGe interface from constant gate biasing can be suppressed by scaling the thickness of Y ₂ O ₃ .

中文翻译：

---

采用三甲基铝处理的 TiN/Y₂O₃ 栅极堆叠的等效氧化物厚度缩放对 SiGe MOS 界面性能的影响

研究了使用三甲基铝 (TMA) 处理的 TiN/Y ₂ O ₃ /SiGe 栅极堆叠的超薄等效氧化物厚度 (EOT) 缩放 。与之前报道的使用各种 Ge 含量的高 k/SiGe MOS 界面相比，我们获得了一个缩小到 1 nm 的 EOT，具有超低的界面陷阱密度（ $\text{D}_{\text {it}}$ ）。此外，还研究了 EOT 缩放对 SiGe MOS 界面特性的影响。我们发现可以通过缩放 Y ₂ O ₃的厚度来抑制来自恒定栅极偏置的 SiGe 界面处的应力引起的退化 。