As device integration density increases exponentially as predicted by Moore’s law, power consumption becomes a bottleneck for system scaling where leakage power of on-chip cache occupies a large fraction of the total power budget. Spin transfer torque magnetic random access memory (STT-MRAM) is a promising candidate to replace static random access memory (SRAM) as an on-chip last level cache (LLC) due to its ultralow leakage power, high integration density, and nonvolatility. Moreover, with the prevalence of edge computing and Internet-of-Things (IoT) applications, it can be beneficial to build a total nonvolatile cache hierarchy, including the L1 cache. However, building an L1 cache with STT-MRAM still faces severe challenges particularly because reducing its relatively high write latency by increasing write voltage can accelerate oxide breakdown of the MTJ device and threaten the L1 cache lifetime significantly due to intensive accesses. In our previous work, we proposed a dynamic overwriting voltage adjustment (DOVA) technique to deal with this challenge. In this article, we improve this technique by a DOVA promotion (DOVA PRO) technique for the STT-MRAM L1 cache, considering the cache write endurance and performance simultaneously. A high write voltage is used for performance-critical cache lines, while a low write voltage is used for other cache lines to approach an optimal tradeoff between reliability and performance. Experimental results show that the proposed technique DOVA PRO can improve cache performance by 23.5%, on average, compared to the DOVA technique. In the meantime, the average degradation of cache lifetime remains almost unchanged compared with the DOVA technique on average. Furthermore, DOVA PRO can support flexible configurations to achieve various optimization targets, such as higher performance or a longer lifetime.

中文翻译：

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DOVA PRO：一种考虑介电击穿效应的STT-MRAM L1缓存动态改写电压调整技术

随着摩尔定律预测的器件集成密度呈指数增长，功耗成为系统扩展的瓶颈，其中片上缓存的泄漏功率占据总功耗预算的很大一部分。自旋转移矩磁随机存取存储器 (STT-MRAM) 由于其超低泄漏功率、高集成密度和非易失性，是替代静态随机存取存储器 (SRAM) 作为片上末级缓存 (LLC) 的有希望的候选者。此外，随着边缘计算和物联网 (IoT) 应用程序的普及，构建包括 L1 缓存在内的完整非易失性缓存层次结构可能是有益的。然而，使用 STT-MRAM 构建 L1 缓存仍然面临严峻挑战，特别是因为通过增加写入电压来降低其相对较高的写入延迟会加速 MTJ 器件的氧化物击穿，并由于密集访问而显着威胁 L1 缓存寿命。在我们之前的工作中，我们提出了一种动态覆盖电压调整 (DOVA) 技术来应对这一挑战。在本文中，我们通过针对 STT-MRAM L1 缓存的 DOVA 提升 (DOVA PRO) 技术改进此技术，同时考虑缓存写入耐久性和性能。高写入电压用于性能关键的缓存线，而低写入电压用于其他缓存线，以在可靠性和性能之间取得最佳平衡。实验结果表明，与DOVA技术相比，所提出的技术DOVA PRO可以将缓存性能平均提高23.5%。同时，与 DOVA 技术相比，缓存寿命的平均退化几乎保持不变。此外，DOVA PRO 可以支持灵活的配置以实现各种优化目标，例如更高的性能或更长的寿命。