In this brief, we propose a logarithmic converter for floating-point numbers based on the piecewise linear (PWL) approximation method. The proposed method is applicable to any customized floating-point format with a mantissa length of 16–23 bits and a maximum absolute error (MAE) larger than 10 ⁻⁶ . The logarithmic function is automatically segmented into several maximal subsections by a software-based segmentation scheme with the restriction of a predefined MAE and a fractional word length for the computing units. Then, we make a tradeoff between the piecewise number and the fractional word length. Based on the results of the segmentor, our design is coded in the Verilog hardware description language. The synthesized results show that our design consumes less area, time, and power without compromising accuracy compared to existing techniques based on the COordinate Rotation Digital Computer (CORDIC) and PWL methods.

中文翻译：

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基于 PWL 的浮点数对数计算架构

在这个简介中，我们提出了一种基于分段线性 (PWL) 近似方法的浮点数对数转换器。所提出的方法适用于尾数长度为 16-23 位且最大绝对误差 (MAE) 大于 10 ^{-6 的}任何自定义浮点格式 . 对数函数通过基于软件的分割方案自动分割成几个最大的子部分，并限制了预定义的 MAE 和计算单元的小数字长。然后，我们在分段数和小数字长之间进行权衡。基于分割器的结果，我们的设计以 Verilog 硬件描述语言进行编码。综合结果表明，与基于坐标旋转数字计算机 (CORDIC) 和 PWL 方法的现有技术相比，我们的设计在不影响精度的情况下消耗更少的面积、时间和功率。