Embedded static random access memories (SRAMs) with cost-effective test screening circuitry are demonstrated for low-power microcontroller units (MCUs). The probing test step at the low temperature (LT) of −40 °C is obviated by imitating pseudo-LT (PLT) conditions in the package test, where a sample is measured at room temperature (RT). Monte Carlo simulation is carried out considering local $V_{\mathrm {t}}$ variations as well as contact soft open failure (high resistance), confirming good minimum operating voltage ( $V_{\mathrm {min}}$ ) correlation between LT and PLT conditions. Test chips with two types of 4-Mbit single-port SRAM macros and 1-Mbit dual-port SRAM macro are designed and fabricated using low-power 40-nm CMOS technology. Measurement results demonstrate that the proposed test method reproduces LT conditions and screens out LT failures with less overscreening. The proposed test method eliminates 1/3 or more of the test costs.

中文翻译：

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用于低功耗 MCU 的 40-nm 嵌入式 SRAM 的经济高效的测试筛选方法

针对低功耗微控制器单元 (MCU) 演示了具有成本效益测试筛选电路的嵌入式静态随机存取存储器 (SRAM)。通过模仿封装测试中的伪 LT (PLT) 条件，在室温 (RT) 下测量样品，避免了 -40 °C 低温 (LT) 下的探测测试步骤。蒙特卡罗模拟考虑局部 $V_{\mathrm {t}}$ 变化以及接触软开故障（高电阻），确认良好的最小工作电压（ $V_{\mathrm {min}}$ ) LT 和 PLT 条件之间的相关性。使用低功耗 40-nm CMOS 技术设计和制造具有 4-Mbit 单端口 SRAM 宏和 1-Mbit 双端口 SRAM 宏两种类型的测试芯片。测量结果表明，所提出的测试方法重现了 LT 条件并以较少的过度筛选来筛选出 LT 故障。建议的测试方法消除了 1/3 或更多的测试成本。