Abstract As the technology node continues to scale, soft errors have become a major issue for reliable processor designs. In this paper, we propose a framework that accurately and efficiently estimates the Architectural Vulnerability Factor (AVF) of critical storage structures of a processor. The proposed approach exploits the masking effects between array structure (e.g., register files and Caches) and logic units (e.g., Int-ALU) via the unified Probabilistic Graphical Models (PGM) methodology, and can provide guaranteed AVFs by two accuracy–efficiency tradeoff solutions. The experimental results have confirmed that, compared to current state-of-the-art approaches, the proposed framework achieves accurate and efficient estimation via two instanced solutions: (1) first-order masking effects up to 45.96% and on average 8.48% accuracy improvement with 52.01× speedup; (2) high-order masking effects average 87.28% accuracy improvement with 43.87× speedup. The two different accuracy–efficiency tradeoff of proposed MEA-PGM can be applied into different estimation scenarios (e.g., short time to market of general mobile devices and high reliable requirements in aerospace platforms) in flexibility.

中文翻译：

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通过概率图形模型利用组件依赖性进行准确有效的软错误分析

摘要 随着技术节点的不断扩展，软错误已成为可靠处理器设计的主要问题。在本文中，我们提出了一个框架，可以准确有效地估计处理器关键存储结构的架构脆弱性因子 (AVF)。所提出的方法通过统一的概率图形模型 (PGM) 方法利用阵列结构（例如，寄存器文件和缓存）和逻辑单元（例如，Int-ALU）之间的掩蔽效应，并且可以通过两种精度-效率权衡来提供有保证的 AVF解决方案。实验结果证实，与当前最先进的方法相比，所提出的框架通过两个实例化解决方案实现了准确有效的估计：（1）一阶掩蔽效应高达 45.96%，平均为 8。精度提高 48%，加速比提高 52.01 倍；(2) 高阶掩蔽效果平均精度提高 87.28%，加速比提高 43.87 倍。提议的 MEA-PGM 的两种不同的精度-效率权衡可以灵活地应用于不同的估计场景（例如，通用移动设备的上市时间短和航空航天平台的高可靠性要求）。