The current era of ubiquitous computing has led to the emergence of a sub-domain in cryptography called Lightweight Cryptography, which deals with imparting adequate security to resource constraint devices like IoT devices, RFID tags with a suitable choice of design metrics. The advancement in network connectivity and data handling capabilities shows the tremendous growth of IoT in physical life. The number of connected devices have been increasing throughout IoT applications, leaving severe security concerns behind. There is a need of secure communication which can be fulfilled with lightweight algorithms. The motive of this work is to implement the optimized lightweight ciphers and model its design metrics. Design has to be simulated to implement the cipher in hardware from which different metrics can be measured. TEA, XTEA and XXTEA ciphers have been used to fulfil the objective stated and were modelled, implemented and optimized on specific hardware technology like Field Programmable Gate Array (FPGA) and Application Specific Integrated Circuit (ASIC) platform. Designs have been implemented to examine numerous properties like block sizes, rounds of implementations and key scheduling part. This paper presents four hardware architectures namely TEA (T1), XTEA (T2), XXTEA (T3) and hybrid model (T4). T1, T2 and T3 have been implemented using pipelined method with percentage improvement in frequency is 75.9%, 162% and 89%. Similarly, the enhancement in terms of area has been 85.43%, 57.08% and 90.79%. T4 presents a hybrid model which is also a pipelined architecture that combines TEA family (TEA, XTEA and XXTEA) in a single design. The percentage improvement of gate equivalent (GE) for T2 is 47.50%. The hybrid model (T4) has the same throughput as that of T1, T2 & T3 and has less GE when compared to combined GE of all three. Efficiency improvement of all the novel architectures are more than eighteen times as compared to the existing literature.

当前无处不在的计算时代导致了密码学子域的出现，称为轻量级密码学，该子域处理为物联网设备、RFID 标签等资源受限设备提供足够的安全性，并选择合适的设计指标。网络连接和数据处理能力的进步表明物联网在物理生活中的巨大增长。在整个物联网应用中，连接设备的数量一直在增加，留下了严重的安全问题。需要使用轻量级算法来实现安全通信。这项工作的动机是实现优化的轻量级密码并对其设计指标进行建模。必须模拟设计以在硬件中实现密码，从中可以测量不同的指标。茶，XTEA 和 XXTEA 密码已用于实现既定目标，并在现场可编程门阵列 (FPGA) 和专用集成电路 (ASIC) 平台等特定硬件技术上进行建模、实施和优化。已实施设计以检查许多属性，例如块大小、实施轮次和关键调度部分。本文介绍了四种硬件架构，即TEA（T1）、XTEA（T2）、XXTEA（T3）和混合模型（T4）。T1、T2 和 T3 已使用流水线方法实现，频率提高百分比分别为 75.9%、162% 和 89%。同样，面积方面的增强分别为85.43%、57.08%和90.79%。T4 提出了一种混合模型，它也是一种将 TEA 系列（TEA、XTEA 和 XXTEA）组合在一个设计中的流水线架构。T2 的门等效 (GE) 改进百分比为 47.50%。混合模型 (T4) 具有与 T1、T2 和 T3 相同的吞吐量，并且与所有三者的组合 GE 相比具有更少的 GE。与现有文献相比，所有新颖架构的效率提高了 18 倍以上。