This paper proposes a novel framework to design efficient variable-latency speculative adders based on a method that mixes serial/parallel prefix structures. In comparison to the conventional speculative parallel prefix adders, the proposed method eliminates the dependency of error signals, and the corresponding late completion error correction. In comparison to conventional variable latency speculative parallel prefix adders, the proposed method reduces energy-consumption by avoiding overlap in the processing of the sub-adders, overcoming the application of double prefix cell and duplicated gates. Moreover, with the proposed method, instead of having an error detection and correction circuit for low-probability errors, serial concatenations of sub-adders are considered for the worst-case. Experimental results show significant improvements in the Area-Delay Product (ADP) and Power-Delay Product (PDP) in comparison to the state-of-the-art variable latency speculative designs.

本文提出了一种新颖的框架，以基于混合串行/并行前缀结构的方法来设计高效的可变延迟推测加法器。与传统的推测性并行前缀加法器相比，所提出的方法消除了错误信号的依赖性，以及相应的延迟完成纠错。与传统的可变延迟推测并行前缀加法器相比，所提出的方法通过避免子加法器处理中的重叠、克服双前缀单元和重复门的应用来降低能量消耗。此外，使用所提出的方法，代替具有用于低概率错误的错误检测和校正电路，在最坏情况下考虑子加法器的串行级联。