Microprocessor design, debug, and validation research and development are increasingly based on modeling and simulation at different abstraction layers. Microarchitecture-level simulators have become the most commonly used tools for performance evaluation, due to their high simulation throughput, compared to lower levels of abstraction, but usually come at the cost of loss of hardware accuracy. As a result, the implementation, speed, and accuracy of microarchitectural simulators are becoming more and more crucial for researchers and microprocessor architects. One of the most critical aspects of a microarchitectural simulator is its ability to accurately express design standards as various aspects of the microarchitecture change during design refinement. On the other hand, modern microprocessor models rely on dedicated hardware implementations, making the design space exploration a time-consuming process that can be performed using a variety of methods, ranging from high-level models to hardware prototyping. Therefore, the tradeoff between simulation speed and accuracy, can be significantly varied, and an application's performance measurements uncertain. In this paper, we present a microarchitecture-level simulation modeling study, which enables as accurate as possible performance modeling of a RISC-V out-of-order superscalar microprocessor core. By diligently adjusting several important microarchitectural parameters of the widely used gem5 simulator, we investigate the challenges of accurate performance modeling on microarchitecture-level simulation compared to accuracy and low simulation throughput of RTL simulation of the target design. Further, we demonstrate the main sources of errors that prevent high accuracy levels of the microarchitecture-level modeling.

中文翻译：

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实现 RISC-V 设计的准确性能建模

微处理器设计、调试和验证研究和开发越来越多地基于不同抽象层的建模和仿真。与较低的抽象级别相比，微架构级模拟器已成为最常用的性能评估工具，因为它们具有较高的模拟吞吐量，但通常以损失硬件精度为代价。因此，微架构模拟器的实现、速度和准确性对研究人员和微处理器架构师来说变得越来越重要。微架构模拟器最关键的方面之一是它能够准确地表达设计标准，因为在设计改进过程中微架构的各个方面都会发生变化。另一方面，现代微处理器模型依赖于专用硬件实现，使设计空间探索成为一个耗时的过程，可以使用各种方法来执行，从高级模型到硬件原型。因此，仿真速度和精度之间的权衡可能会发生很大变化，并且应用程序的性能测量结果不确定。在本文中，我们提出了一项微体系结构级仿真建模研究，它可以对 RISC-V 乱序超标量微处理器内核进行尽可能准确的性能建模。通过认真调整广泛使用的 gem5 模拟器的几个重要微架构参数，我们研究了与目标设计的 RTL 仿真的准确性和低仿真吞吐量相比，微架构级仿真的准确性能建模面临的挑战。更多，