FPGA is widely used as hardware accelerator to improve the performance of convolutional neural network (CNN). Performance of CNN can be improved by increasing the throughput of convolution layer using any parallelism technique/s, as convolution operation occupies around ninety percent of total computations in CNN. Usually a CNN model will be configured to support one of the dominant parallelism styles (feature map parallelism (FP), synapse parallelism (SP) and neuron parallelism (NP)). Since each of these parallelism styles has different data flow architectures, a CNN model will support one particular parallelism type only. The work focuses on realizing data flows for all the three dominant parallelism styles with a single architecture of convolution layer using System Verilog. Proposed data flows of SP, NP and FP is synthesized and the results obtained indicates that this proposed approach provides better results when compared to convolution layer implemented with data flows of dominant parallelism styles [19] and data flow without parallelism.

FPGA 被广泛用作硬件加速器以提高卷积神经网络 (CNN) 的性能。可以通过使用任何并行技术增加卷积层的吞吐量来提高 CNN 的性能，因为卷积操作占 CNN 总计算量的 90% 左右。通常，CNN 模型会被配置为支持一种主要的并行性风格（特征图并行性 (FP)、突触并行性 (SP) 和神经元并行性 (NP)）。由于这些并行样式中的每一种都具有不同的数据流架构，因此 CNN 模型将仅支持一种特定的并行类型。这项工作的重点是使用 System Verilog 使用卷积层的单一架构实现所有三种主要并行样式的数据流。建议的 SP 数据流，