Fast SC decoding overcomes the latency caused by the serial nature of the SC decoding by identifying new nodes in the upper levels of the SC decoding tree and implementing their fast parallel decoders. In this work, we first present a novel sequence repetition node corresponding to a particular class of bit sequences. Most existing special node types are special cases of the proposed sequence repetition node. Then, a fast parallel decoder is proposed for this class of node. To further speed up the decoding process of general nodes outside this class, a threshold-based hard-decision-aided scheme is introduced. The threshold value that guarantees a given error-correction performance in the proposed scheme is derived theoretically. Analysis and hardware implementation results on a polar code of length 1024 with code rates 1/4, 1/2, and 3/4 show that our proposed algorithm reduces the required clock cycles by up to 8%, and leads to a 10% improvement in the maximum operating frequency compared to state-of-the-art decoders without tangibly altering the error-correction performance. In addition, using the proposed threshold-based hard-decision-aided scheme, the decoding latency can be further reduced by 57% at $\mathrm {E_{b}}/\mathrm {N_{0}} = 5.0$ dB.

中文翻译：

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基于阈值的极性码快速逐次对消解码

快速 SC 解码通过识别 SC 解码树上层中的新节点并实现它们的快速并行解码器，克服了由 SC 解码的串行性质引起的延迟。在这项工作中，我们首先提出了一个新的序列重复节点，对应于特定类别的位序列。大多数现有的特殊节点类型是提议的序列重复节点的特例。然后，针对此类节点提出了一种快速并行解码器。为了进一步加快此类以外的一般节点的解码过程，引入了一种基于阈值的硬决策辅助方案。在所提出的方案中保证给定纠错性能的阈值是从理论上推导出来的。长度为1024、码率1/4、1/2、和 3/4 表明，与最先进的解码器相比，我们提出的算法将所需的时钟周期减少了多达 8%，并使最大工作频率提高了 10%，而没有明显改变纠错性能. 此外，使用所提出的基于阈值的硬决策辅助方案，解码延迟可以进一步减少 57% $\mathrm {E_{b}}/\mathrm {N_{0}} = 5.0$ D b。