Abstract The paper presents the developed complex Digital Signal Processing algorithm for the reduction of white and 1/f noise and processing of the measurement signals of the Settling Time Measurement of the Digital-to-Analog Converters. The results show that the proposed DSP algorithm ensures 100-fold suppression of the white noise and 1/f noise. It was shown that it is possible to measure settling times of highspeed DACs (up to 16-17 Bits) with readout levels of ± 0.5 LSB while measurement errors do no exceed ± 1.4 ns.

中文翻译：

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用于测量高分辨率高速 DAC 建立时间的数字信号处理算法

摘要 本文介绍了已开发的复杂数字信号处理算法，用于降低白噪声和 1/f 噪声以及处理数模转换器建立时间测量的测量信号。结果表明，所提出的DSP算法保证了对白噪声和1/f噪声的100倍抑制。结果表明，可以测量高速 DAC（高达 16-17 位）的稳定时间，读出电平为 ± 0.5 LSB，而测量误差不超过 ± 1.4 ns。