Digital computation using multi-valued logic decreases the requirement of interconnections which leads to a reduction in the power consumption, energy consumption and chip area in digital system design. Among various sequential logic elements, a counter is the main block that is repeatedly used for counting purposes in several processor applications. This work presents the methodology to design asynchronous and synchronous counter designs using three valued logic. The circuit implementation includes shifting operators for the D-flip-flop and counter realization in carbon nanotube technology. To realize optimized shifting circuits efficient voltage divider topology is employed by exploiting the most appropriate on-state current capability of active P-type and N-type transistors. The unique characteristic of carbon nanotube field-effect transistors (CNTFETs) to control the threshold voltage of the device by adjusting the CNT diameter favors their suitability for ternary design implementation. Thereafter, for the performance assessment of the proposed designs, simulations are conducted using the 32 nm CNTFET model using the Synopsys HSPICE simulator. Simulation results confirm the reduction in power consumption and Power delay product(PDP) of 51% and 69% for 3-bit asynchronous counter and 46% and 47% respectively for 2-bit synchronous counter design. Also, the proposed counter design shows the satisfactory operation and works reliably when simulated under different test conditions of temperature, voltage, and process variations.

使用多值逻辑的数字计算降低了互连的要求，从而降低了数字系统设计中的功耗、能耗和芯片面积。在各种时序逻辑元件中，计数器是主要块，在多个处理器应用中重复用于计数目的。这项工作介绍了使用三值逻辑设计异步和同步计数器设计的方法。电路实现包括用于 D 触发器的移位运算符和碳纳米管技术中的计数器实现。为了实现优化的移位电路，通过利用有源 P 型和 N 型晶体管的最合适的导通电流能力，采用了高效的分压器拓扑结构。碳纳米管场效应晶体管 (CNTFET) 通过调整 CNT 直径来控制器件阈值电压的独特特性有利于它们适用于三元设计实现。此后，为了对建议的设计进行性能评估，使用 Synopsys HSPICE 仿真器的 32 nm CNTFET 模型进行仿真。仿真结果证实，3 位异步计数器的功耗和功率延迟积 (PDP) 分别降低了 51% 和 69%，2 位同步计数器设计分别降低了 46% 和 47%。此外，在不同温度、电压和工艺变化的测试条件下进行模拟时，所提出的计数器设计显示出令人满意的操作并可靠地工作。