In this study, new multiplier and adder method designs with multiplexers are proposed. The designs are based on quaternary logic and a carbon nanotube field-effect transistor (CNTFET). The design utilizes 4 × 4 multiplier blocks. Applying specific rotational functions and unary operators to the quaternary logic reduced the power delay produced (PDP) circuit by 54% and 17.5% in the CNTFETs used in the adder block and by 98.4% and 43.62% in the transistors in the multiplier block, respectively. The proposed 4 × 4 multiplier also reduced the occupied area by 66.05% and increased the speed circuit by 55.59%. The proposed designs are simulated using HSPICE software and 32 nm technology in the Stanford Compact SPICE model for CNTFETs. The simulated results display a significant improvement in the fabrication, average power consumption, speed, and PDP compared to the current best-performing techniques in the literature. The proposed operators and circuits are evaluated under various operating conditions, and the results demonstrate the stability of the proposed circuits.

中文翻译：

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具有碳纳米管场效应晶体管的低能量和面积高效的四元乘法器

在这项研究中，提出了带有多路复用器的新乘法器和加法器方法设计。这些设计基于四元逻辑和碳纳米管场效应晶体管 (CNTFET)。该设计使用 4 × 4 乘法器模块。将特定的旋转函数和一元运算符应用于四进制逻辑，在加法器块中使用的 CNTFET 中，功率延迟产生 (PDP) 电路分别减少了 54% 和 17.5%，在乘法器块中的晶体管中分别减少了 98.4% 和 43.62% . 提议的 4 × 4 乘法器也将占用面积减少了 66.05%，并将速度电路增加了 55.59%。提议的设计是使用 HSPICE 软件和 32 nm 技术在用于 CNTFET 的斯坦福 Compact SPICE 模型中进行仿真的。模拟结果显示在制造、平均功耗、速度、和 PDP 与文献中当前表现最佳的技术相比。在各种操作条件下对所提出的算子和电路进行了评估，结果证明了所提出电路的稳定性。