Purpose Analysis of the thermal effects during the packaging process or in the actual operating environment is necessary to develop small monolithic integrated sensing chips with heterogeneous integration. The use of multiple layers and various materials in monolithic integrated sensing chips addresses the coefficient of thermal expansion (CTE) mismatch issue. The purpose of this study is to focus on the residual stress analysis of the shielding electrode, which is a metal film that prevents pull-in of proof-mass during anodic bonding in microelectromechanical system (MEMS) chips with pressure sensors embedded in an accelerometer. Design/methodology/approach The finite element model of the chip was built by the commercial software ANSYS, and the residual stress was evaluated during the die attachment process for the shielding electrode. Various shielding electrode materials and a proposed design with a keep-out zone to reduce the residual stress are discussed, with a focus on the relationship between the geometric parameters of the chip and the residual stress for copper shielding electrodes of different thicknesses. Findings The results of the finite element analysis showed that the use of polysilicon as a shielding electrode in the proposed design generated the lowest residual stress because of its low CTE. The maximum stresses in both of in-plane and out-of-plane directions in the finite element model were reduced by keep-out zone design for the proposed design of the copper shielding electrode, and had 11 times reduction in out-of-plane direction especially, according to the nonlinear analysis as the stress concentration point in the shielding electrode moved. Moreover, the design with a thinner shielding electrode, thinner glass substrate and higher CTE of the glass substrate also lowered the maximum von Mises stress. On the other hand, the stress level during the operating temperature, without considering residual stress, overestimated up to five times in the proposed design. Originality/value In this study, valuable suggestions are proposed for the design of chips with pressure sensors embedded in accelerometers.

中文翻译：

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加速度计内嵌压力传感器芯片屏蔽电极应力分析

目的分析封装过程中或实际运行环境中的热效应是开发具有异构集成的小型单片集成传感芯片所必需的。在单片集成传感芯片中使用多层和各种材料解决了热膨胀系数 (CTE) 失配问题。本研究的目的是关注屏蔽电极的残余应力分析，屏蔽电极是一种金属薄膜，可防止在带有嵌入加速度计的压力传感器的微机电系统 (MEMS) 芯片的阳极键合过程中引入质量块。设计/方法/途径芯片的有限元模型由商业软件ANSYS建立，并在屏蔽电极的贴片过程中评估残余应力。讨论了各种屏蔽电极材料和建议的带有隔离区以减少残余应力的设计，重点是芯片的几何参数与不同厚度铜屏蔽电极的残余应力之间的关系。结果 有限元分析的结果表明，在提议的设计中使用多晶硅作为屏蔽电极会产生最低的残余应力，因为它的 CTE 低。有限元模型中平面内和平面外方向的最大应力通过铜屏蔽电极的建议设计的禁区设计降低，平面外减少了11倍特别是方向，根据非线性分析，随着屏蔽电极中的应力集中点移动。而且，更薄的屏蔽电极、更薄的玻璃基板和更高的玻璃基板 CTE 的设计也降低了最大 von Mises 应力。另一方面，在不考虑残余应力的情况下，工作温度期间的应力水平在拟议设计中高估了五倍。原创性/价值 在这项研究中，为设计带有嵌入加速度计的压力传感器的芯片提出了有价值的建议。