Purpose

In this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.

Design/methodology/approach

The modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.

Findings

Both RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.

Originality/value

The DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

中文翻译：

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用于软件定义无线电信道器应用的优化 DA 可重构 FIR 滤波器

目的

在本文中，作者介绍了可重构有限脉冲响应 (RFIR) 滤波器设计的不同方法。基于分布式算术 (DA) 的可重构 FIR 滤波器设计适用于软件定义无线电 (SDR) 应用。重新配置的主要贡献是重用寄存器、乘法器、加法器，并优化各种参数，例如面积、功耗、速度、吞吐量、延迟和触发器和片的硬件利用率。因此，将针对具有上述所有参数的 RFIR 滤波器优化构建模块的有效设计。

设计/方法/方法

FIR 滤波器修改后的直接形式寄存器结构有助于重用概念，并允许使用较少数量的寄存器和并行计算操作。DA 和其他传统方法的缺点是延迟与滤波器长度成比例增加。这是由于加法器产生不同的部分积。DA-FIR 滤波器中加法器和乘法器的使用限制了面积和功耗，因为它们生成和和进位位的复杂性。基于Ling方程的并行前缀加法器（PPA）使用可以减少加法器的硬件实现时间。PPA 使用移位加乘法，这是一个重复的加法过程，这个过程在直接乘法中被称为旁路零馈入被乘数，所提出的技术有效地优化了面积功率积。基于改进型 DA (MDA) 的 RFIR 滤波器设计用于 64 抽头滤波器长度 (N)。该设计采用 Verilog 硬件描述语言开发，并在现场可编程门阵列上实现。此外，此设计验证了 SDR 通道均衡器。

发现

RFIR 和 SDR 均集成为单一系统，并在 XC7A100tCSG324 的 Artix-7 开发板上实现，充分发挥了在面积延迟、功率速度产品和能效方面的优势。进行了理论和实际对比，结果与现有DA-RFIR设计在吞吐量、时延、面积延迟、功率速度积和能效方面进行了比较，分别提高了14.5%、23%、分别为 6.5%、34.2% 和 21%。

原创性/价值

基于 DA 的 RFIR 滤波器使用 Xilinx ISE 设计套件中的 Artix-7 FPGA 上的 Chipscope Pro 软件工具进行验证，并将约束参数与现有的最新结果进行比较。还测试了通过对音频信号应用 RFIR 滤波器去除噪声信号的滤波操作，发现 95% 的噪声信号被有效过滤。