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Filling efficiency of flip-chip underfill encapsulation process
Soldering & Surface Mount Technology ( IF 2 ) Pub Date : 2019-10-07 , DOI: 10.1108/ssmt-07-2019-0026
Fei Chong Ng , Mohamad Aizat Abas , Mohd Zulkifly Abdullah

This paper aims to introduce a new indicative parameter of filling efficiency to quantify the performance and productivity of the flip-chip underfill encapsulation process. Additionally, the variation effect of the bump pitch of flip-chip on the filling efficiency was demonstrated to provide insight for flip-chip design optimization.,The filling efficiency was formulated analytically based on the conceptual spatial and temporal perspectives. Subsequently, the effect of bump pitch on filling efficiency was studied based on the past actual-scaled and current scaled-up underfill experiments. The latter scaled-up experiment was validated with both the finite volume method-based numerical simulation and analytical filling time model. Moreover, the scaling validity of scaled-up experiment was justified based on the similarity analysis of dimensionless number.,Through the scaling analysis, the current scaled-up experimental system is justified to be valid since the adopted scaling factor 40 is less than the theoretical scaling limit of 270. Furthermore, the current experiment was qualitatively well validated with the numerical simulation and analytical filling time model. It is found that the filling efficiency increases with the bump pitch, such that doubling the bump pitch would triple the efficiency.,The new performance indicative index of filling efficiency enables the package designers to justify the variation effect of underfill parameter on the overall underfill process. Moreover, the upper limit of scaling factor for scaled-up package was derived to serve as the guideline for future scaled-up underfill experiments.,The performance of underfill process as highlighted in this paper was never being quantified before in the past literatures. Similarly, the scaling limit that is associated to the scaled-up underfill experiment was never being reported elsewhere too.

中文翻译:

倒装芯片底部填充封装工艺的填充效率

本文旨在引入一种新的填充效率指示参数,以量化倒装芯片底部填充封装工艺的性能和生产率。此外,还证明了倒装芯片凸点间距对填充效率的变化影响,为倒装芯片设计优化提供了见解。填充效率是基于概念空间和时间的角度分析制定的。随后,基于过去的实际放大和当前放大底部填充实验,研究了凸块间距对填充效率的影响。后者的放大实验得到了基于有限体积法的数值模拟和分析填充时间模型的验证。而且,基于无量纲数的相似性分析,证明了放大实验的缩放有效性。,通过缩放分析,当前的放大实验系统被证明是有效的,因为采用的缩放因子40小于理论缩放限制270。此外,当前实验定性地很好地验证了与数值模拟和分析填充时间模型。发现填充效率随着凸块间距的增加而增加,因此将凸块间距加倍会使效率提高三倍。填充效率的新性能指标使封装设计人员能够证明底部填充参数的变化对整个底部填充工艺的影响. 而且,推导出按比例放大封装的比例因子上限,作为未来按比例放大底部填充实验的指南。本文中强调的底部填充工艺的性能在过去的文献中从未被量化过。同样,与放大底部填充实验相关的缩放限制也从未在其他地方报道过。
更新日期:2019-10-07
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