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A graph placement methodology for fast chip design
Nature ( IF 42.778 ) Pub Date : 2021-06-09 , DOI: 10.1038/s41586-021-03544-w
Azalia Mirhoseini, Anna Goldie, Mustafa Yazgan, Joe Wenjie Jiang, Ebrahim Songhori, Shen Wang, Young-Joon Lee, Eric Johnson, Omkar Pathak, Azade Nazi, Jiwoo Pak, Andy Tong, Kavya Srinivasa, William Hang, Emre Tuncer, Quoc V. Le, James Laudon, Richard Ho, Roger Carpenter, Jeff Dean

Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research1, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcement learning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google’s artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields.



中文翻译:

一种用于快速芯片设计的图形放置方法

芯片布局规划是设计计算机芯片物理布局的工程任务。尽管经过了五年的研究1, 芯片布局规划已经无视自动化,需要物理设计工程师花费数月的大量努力来生产可制造的布局。在这里,我们提出了一种用于芯片布局规划的深度强化学习方法。在不到六小时的时间内,我们的方法会自动生成在所有关键指标(包括功耗、性能和芯片面积)上都优于或可与人类生成的芯片布局图相媲美的芯片布局图。为了实现这一点,我们将芯片布局规划作为一个强化学习问题,并开发了一种基于边的图卷积神经网络架构,能够学习芯片的丰富且可转移的表示。因此,我们的方法利用过去的经验来更好更快地解决问题的新实例,允许芯片设计由比任何人类设计师都有更多经验的人工代理执行。我们的方法被用于设计下一代谷歌人工智能 (AI) 加速器,并且有可能为每一代人节省数千小时的人力。最后,我们相信更强大的人工智能设计硬件将推动人工智能的进步,在两个领域之间建立共生关系。

更新日期:2021-06-09
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