Chip floorplanning is the engineering task of designing the physical layout of a computer chip. Despite five decades of research¹, chip floorplanning has defied automation, requiring months of intense effort by physical design engineers to produce manufacturable layouts. Here we present a deep reinforcement learning approach to chip floorplanning. In under six hours, our method automatically generates chip floorplans that are superior or comparable to those produced by humans in all key metrics, including power consumption, performance and chip area. To achieve this, we pose chip floorplanning as a reinforcement learning problem, and develop an edge-based graph convolutional neural network architecture capable of learning rich and transferable representations of the chip. As a result, our method utilizes past experience to become better and faster at solving new instances of the problem, allowing chip design to be performed by artificial agents with more experience than any human designer. Our method was used to design the next generation of Google’s artificial intelligence (AI) accelerators, and has the potential to save thousands of hours of human effort for each new generation. Finally, we believe that more powerful AI-designed hardware will fuel advances in AI, creating a symbiotic relationship between the two fields.

芯片布局规划是设计计算机芯片物理布局的工程任务。尽管经过了五年的研究¹，芯片布局规划仍然无法实现自动化，需要物理设计工程师花费数月的时间进行大量努力才能产生可​​制造的布局。在这里，我们提出了一种用于芯片布局规划的深度强化学习方法。在不到六个小时的时间内，我们的方法自动生成了芯片布局图，该布局图在所有关键指标（包括功耗、性能和芯片面积）上都优于或与人类生成的布局图相当。为了实现这一目标，我们将芯片布局规划视为强化学习问题，并开发了一种基于边缘的图卷积神经网络架构，能够学习丰富且可转移的芯片表示。因此，我们的方法利用过去的经验来更好更快地解决问题的新实例，从而允许比任何人类设计师更有经验的人工代理来执行芯片设计。我们的方法被用来设计下一代谷歌人工智能（AI）加速器，并且有可能为每一代节省数千小时的人力。最后，我们相信更强大的人工智能设计硬件将推动人工智能的进步，在两个领域之间建立共生关系。