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Strain relaxation in semiconductor wafer bonding
Japanese Journal of Applied Physics ( IF 1.5 ) Pub Date : 2021-05-06 , DOI: 10.35848/1347-4065/abf9e4
Katsuaki Tanabe

The strain relaxation process in wafer-bonded semiconductor heterostructures is numerically investigated, in contrast to those formed by epitaxial growth. A kinetic model of strain relaxation in semiconductor layers is re-established for highly lattice-mismatched heterostructures. Numerical simulations are then performed by using the model to analyze the time evolution of the strain, the strain rate, and the misfit dislocation density. The calculation results present a slow strain relaxation behavior in the lattice-mismatched heterostructures wafer-bonded at lower temperatures than those for epitaxial growth, to suppress the thermodynamically preferred dislocation generation by sustaining the material system at a metastable state. The time constant of strain relaxation in a typical range of wafer bonding temperatures, normalized by the melting temperature, of 0.2–0.4 is found to be 3נ105–2נ1021s for a lattice mismatch of 0.04. This relaxation time contrasts with 14s for the case of heteroepitaxy at a typical normalized temperature of 0.6, thus evidencing the nonequilibrium crystalline stability in wafer bonding.



中文翻译:

半导体晶片键合中的应变松弛

与外延生长形成的应力松弛过程相比,晶片键合半导体异质结构中的应变松弛过程在数值上进行了研究。对于高度晶格失配的异质结构,重新建立了半导体层中应变弛豫的动力学模型。然后通过使用该模型进行数值模拟来分析应变的时间演变、应变率和错配位错密度。计算结果表明,在比外延生长温度更低的温度下,晶格失配异质结晶片键合的应变弛豫行为缓慢,通过将材料系统维持在亚稳态来抑制热力学优选位错的产生。在典型的晶圆键合温度范围内应变弛豫的时间常数,5 –2נ10 21秒,晶格失配为 0.04。该弛豫时间与异质外延在 0.6 的典型归一化温度下的 14 秒形成对比,从而证明晶片键合中的非平衡晶体稳定性。

更新日期:2021-05-06
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