The impact of the interface layer on charge trapping and polarization switching at multiple temperatures is investigated. At high temperatures, a ferroelectric field effect transistor with a metal-ferroelectric-insulator-semiconductor (MFIS) gate-stack shows conventional electron-trapping dominated PBTI (i.e., $\Delta \text{V}_{\mathrm{ t}} > 0$ ), whereas at room temperature, negative threshold voltage shifts ( $\Delta \text{V}_{\mathrm{ t}}$ ) are observed. We demonstrate the relationship between the interface layer and the subsequently deposited ferroelectric layers’ effective permittivity: higher permittivity, consistent with a higher tetragonal phase/lower orthorhombic phase content, is noted when the ferroelectric layer is deposited on hydrogen-terminated silicon. In contrast, an anomalous BTI, consistent with a higher orthorhombic phase content, is observed at lower temperatures when the ferroelectric layer is deposited on oxygen-rich surfaces (SiO ₂ , SiON).

中文翻译：

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界面层对基于Si:HfO ₂的 FeFET器件特性的影响

研究了界面层在多个温度下对电荷俘获和极化转换的影响。在高温下，具有金属 - 铁电 - 绝缘体 - 半导体（MFIS）栅极堆叠的铁电场效应晶体管显示出传统的电子俘获主导的PBTI（即， $\Delta \text{V}_{\mathrm{ t}} > 0$ )，而在室温下，负阈值电压偏移 ( $\Delta \text{V}_{\mathrm{ t}}$ ) 被观察到。我们证明了界面层和随后沉积的铁电层的有效介电常数之间的关系：当铁电层沉积在氢端硅上时，注意到更高的介电常数，与更高的四方相/更低的正交相含量一致。相比之下，当铁电层沉积在富氧表面（SiO ₂ 、SiON）上时，在较低温度下观察到异常 BTI，与较高的正交相含量一致 。