This work describes a hybrid incremental ADC (IADC) with two-capacitor (2-C) successive-approximation registers (SAR) extended counting in two-step operation to achieve high resolution data conversion. The circuits in the first step is acting as a first-order incremental analog-to-digital converter (IADC). Finite impulse response (FIR) DAC is incorporated in the loop filter to reduce the transient voltage step. It is reconfigured as a 2-C SAR to perform extended counting technique in the second step. Only one opamp is re-used in both steps. The hardware is prototyped in $0.18~\mu \text{m}$ CMOS technology, and the hybrid ADC accomplishes a measured DR / SNR / SNDR of 100.2 / 97.1 / 96.6 dB and an input signal bandwidth of 1.2 kHz. Operated at 1.5-V, it consumes $33.2~\mu \text{W}$ , and this achieves a Walden figure-of-merit (FoM) of 0.25 pJ/conversion-step and Schreier FoM of 175.8 dB.

中文翻译：

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具有单个运算放大器和两个电容器 SAR 扩展计数的多步增量模数转换器

这项工作描述了一种混合增量式 ADC (IADC)，它在两步操作中具有两个电容器 (2-C) 逐次逼近寄存器 (SAR) 扩展计数，以实现高分辨率数据转换。第一步中的电路充当一阶增量模数转换器 (IADC)。环路滤波器中包含有限脉冲响应 (FIR) DAC，以减少瞬态电压阶跃。在第二步中，它被重新配置为 2-C SAR 以执行扩展计数技术。在这两个步骤中仅重复使用一个运算放大器。硬件原型在 $0.18~\mu \text{m}$ CMOS 技术和混合 ADC 实现了 100.2 / 97.1 / 96.6 dB 的实测 DR / SNR / SNDR 和 1.2 kHz 的输入信号带宽。工作电压为 1.5V，它消耗 $33.2~\mu \text{W}$ ，这实现了 0.25 pJ/转换步长的 Walden 品质因数 (FoM) 和 175.8 dB 的 Schreier FoM。