In an 8B/10B mode giga-bit-per-second serial data transactions, the de-serialized data is sent to a comma detection and word alignment (CDWA) module to identify the word boundaries, which is a prerequisite in the high-speed transceivers such as PCIe, USB and JESD204B/C. In order to ensure that the comma code (/K/-code) can be correctly detected. Ten 10-bit comma detector cells are adopted in a typical CDWA module, which require a complex circuitry and an enormous power consumption. To overcome these limitations, a low-area and low-power CDWA circuit for JESD204B/C transceiver chip in 8B/10B mode has been proposed in this paper. The bit width of the detector cells can be truncated from 10 to 6 under the condition, that CDWA module can detect a complete comma code correctly. On one hand, the proposed CDWA module is verified with a FPGA development platform with the reduction of the hardware resources and power consumption to 31.72% and 20.11% respectively as compared to the typical structure available. On the other hand, a 10-Gbps transceiver chip with the proposed CDWA module is fabricated with a 55-nm CMOS process and the word alignment function of the proposed module is proved by the measurement results. The area of this transceiver chip including $2\times $ transmitting links and $2\times $ receiving links is 2.89 mm ² , and the power consumption is 467.8 mW, under a maximum data transmission rate of 10 Gbps.

中文翻译：

---

用于 JESD204B/C 控制器的小面积、低功耗逗号检测和字对齐电路

在 8B/10B 模式每秒千兆位的串行数据传输中，反序列化的数据被发送到逗号检测和字对齐 (CDWA) 模块以识别字边界，这是高速传输的先决条件PCIe、USB 和 JESD204B/C 等收发器。为了保证逗号代码（/K/-code）可以被正确检测。典型的CDWA模块采用10个10位逗号检测器单元，电路复杂，功耗大。为了克服这些限制，本文提出了一种适用于 8B/10B 模式的 JESD204B/C 收发器芯片的小面积、低功耗 CDWA 电路。在CDWA模块能够正确检测到一个完整的逗号代码的情况下，检测器单元的位宽可以从10位截断到6位。一方面，所提出的 CDWA 模块通过 FPGA 开发平台进行验证，与可用的典型结构相比，硬件资源和功耗分别降低了 31.72% 和 20.11%。另一方面，采用 55-nm CMOS 工艺制造具有所提出的 CDWA 模块的 10 Gbps 收发器芯片，并且所提出的模块的字对齐功能由测量结果证明。该收发器芯片的面积包括 $2\times $ 传输链接和 $2\times $ 接收链路为2.89 mm ² ，功耗为467.8 mW，最大数据传输速率为10 Gbps。